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參數資料
| 型號： | IS41LV44052 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 4M x 4 DRAM With Fast Page Mode(3.3V,4M x 4 帶快速頁模式動態(tài)RAM(刷新 2K）) |
| 中文描述： | 4米× 4的DRAM與快速頁面模式（3.3伏，4米× 4帶快速頁模式動態(tài)隨機存儲器（刷新2k）的） |
| 文件頁數： | 7/17頁 |
| 文件大?。?/td> | 137K |
| 代理商： | IS41LV44052 |
Integrated Silicon Solution, Inc.
—
1-800-379-4774
Rev. B
01/31/01
7
IS41C4405
X
IS41LV4405
X
S
ERIES
ISSI
AC CHARACTERISTICS
(Continued)
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
-60
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
t
RWL
Write Command to
RAS
Lead Time
(17)
13
—
15
—
ns
t
CWL
Write Command to
CAS
Lead Time
(17, 21)
8
—
10
—
ns
t
WCS
t
DHR
Write Command Setup Time
(14, 17, 20)
Data-in Hold Time (referenced to
RAS
)
0
39
—
—
0
39
—
—
ns
ns
t
ACH
Column-Address Setup Time to
CAS
Precharge during WRITE Cycle
OE
Hold Time from
WE
during
READ-MODIFY-WRITE cycle
(18)
Data-In Setup Time
(15, 22)
Data-In Hold Time
(15, 22)
READ-MODIFY-WRITE Cycle Time
RAS
to
WE
Delay Time during
READ-MODIFY-WRITE Cycle
(14)
CAS
to
WE
Delay Time
(14, 20)
Column-Address to
WE
Delay Time
(14)
Fast Page Mode READ or WRITE
Cycle Time
RAS
Pulse Width
Access Time from
CAS
Precharge
(15)
READ-WRITE Cycle Time
(24)
Data Output Hold after
CAS
LOW
Output Buffer Turn-Off Delay from
CAS
or
RAS
(13,15,19, 24)
Output Disable Delay from
WE
CAS
Setup Time (CBR REFRESH)
(20, 25)
CAS
Hold Time (CBR REFRESH)
( 21, 25)
OE
Setup Time prior to
RAS
during
HIDDEN REFRESH Cycle
Auto Refresh Period
15
—
15
—
ns
t
OEH
8
—
10
—
ns
t
DS
t
DH
t
RWC
t
RWD
0
8
—
—
—
—
0
10
133
77
—
—
—
—
ns
ns
ns
ns
108
64
t
CWD
t
AWD
t
PC
26
39
20
—
—
—
32
47
25
—
—
—
ns
ns
ns
t
RASP
t
CPA
t
PRWC
t
COH
t
OFF
50
—
56
5
0
100K
30
—
—
12
60
—
68
5
0
100K
35
—
—
15
ns
ns
ns
ns
ns
t
WHZ
t
CSR
t
CHR
t
ORD
3
5
8
0
10
—
—
—
3
5
10
0
10
—
—
—
ns
ns
ns
ns
t
REF
2,048 Cycles
4,096 Cycles
—
—
1
32
64
50
—
—
1
32
64
50
ms
t
T
Transition Time (Rise or Fall)
(2, 3)
ns
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: V
IH
= 2.4V, V
IL
= 0.8V (Vcc = 5.0V ±10%);
V
IH
= 2.0V, V
IL
= 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: V
OH
= 2.0V, V
OL
= 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
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|---|---|
| IS41C44054 | 4M x 4 DRAM With Fast Page Mode(5V,4M x 4 帶快速頁模式動態(tài)RAM(刷新 4K）) |
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| IS41C82002 | 2M x 8 DRAM With EDO Page Mode(5V,2M x 8 帶擴展數據輸出頁模式動態(tài)RAM(刷新 2K）) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| IS41LV44052-50J | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:4M x 4 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| IS41LV44052-50JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
| IS41LV44052-50T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
| IS41LV44052-50TI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
| IS41LV44052-60J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
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