- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377551 > IS42S32200-7TI (INTEGRATED SILICON SOLUTION INC) 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM PDF資料下載
參數(shù)資料
| 型號： | IS42S32200-7TI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 2M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86 |
| 封裝： | 0.400 INCH, TSOP2-86 |
| 文件頁數(shù)： | 15/55頁 |
| 文件大?。?/td> | 982K |
| 代理商： | IS42S32200-7TI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁
IS42S32200
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION
Rev. 00B
08/14/03
15
Activating Specific Row Within Specific Bank
DON'T CARE
CLK
COMMAND
ACTIVE
NOP
NOP
t
RCD
T0
T1
T2
T3
T4
READ or
WRITE
OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to
a bank within the SDRAM, a row in that bank must be
“opened.”
This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated
(see
Activating Specific Row Within Specific Bank
).
After opening a row
(issuing an ACTIVE command)
, a READ
or WRITE command may be issued to that row, subject to
the t
RCD
specification. Minimum t
RCD
should be divided by
the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACTIVE
command on which a READ or WRITE command can be
entered. For example, a t
RCD
specification of 20ns with a
125 MHz clock (8ns period) results in 2.5 clocks, rounded
to 3. This is reflected in the following example, which
covers any case where 2 < [t
RCD
(MIN)/t
CK
]
≤
3. (The
same procedure is used to convert other specification
limits from time units to clock cycles).
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active
row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the
same bank is defined by t
RC
.
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE com-
mands to different banks is defined by t
RRD
.
Example: Meeting t
RCD
(MIN) when 2
<
[t
RCD
(min)/t
CK
]
≤
3
CLK
CKE
HIGH - Z
ROW ADDRESS
BANK ADDRESS
CS
RAS
CAS
WE
A0-A10
BA0, BA1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS42S32400B-7TLI | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400B | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400B-6B | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400B-6BL | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400B-6T | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S32200B | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-6T | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II |
| IS42S32200B-6TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-6TL | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II |
| IS42S32200B-6TLI | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。