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參數(shù)資料
| 型號： | IS42S32400B-6TLI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 中文描述： | 4M X 32 SYNCHRONOUS DRAM, 5.4 ns, PDSO86 |
| 封裝： | LEAD FREE, TSOP2-86 |
| 文件頁數(shù)： | 25/60頁 |
| 文件大?。?/td> | 644K |
| 代理商： | IS42S32400B-6TLI |
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Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00G
06/15/06
25
ISSI
IS42S32400B
DON'T CARE
UNDEFINED
CLK
COMMAND
DQ
READ
NOP
NOP
NOP
CAS Latency - 3
t
AC
t
OH
D
OUT
T0
T1
T2
T3
T4
t
LZ
CLK
COMMAND
DQ
READ
NOP
NOP
CAS Latency - 2
t
AC
t
OH
D
OUT
T0
T1
T2
T3
t
LZ
CAS LATENCY
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge n, and the
latency is
m
clocks, the data will be available by clock edge
n +
m. The DQs will start driving as a result of the clock edge
one cycle earlier
(n + m
- 1), and provided that the relevant
access times are met, the data will be valid by clock edge
n +
m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ
command is registered at T0 and the latency is programmed
to two clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in CAS Latency diagrams. The
Allowable Operating Frequency table indicates the operat-
ing frequencies at which each CAS latency setting can be
used.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CAS Latency = 2
CAS Latency = 3
-6
125
166
-7
100
143
Operating Mode
The normal operating mode is selected by setting M7 and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
相關PDF資料 |
PDF描述 |
|---|---|
| IS42S32400B-7B | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400B-7BI | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400B-7BL | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400B-7BLI | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400B-7T | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S32400B-6TL-TR | 功能描述:動態(tài)隨機存取存儲器 128M (4Mx32) 166MHz Commercial Temp RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS42S32400B-6T-TR | 制造商:Integrated Silicon Solution Inc 功能描述:IC SDRAM 128MBIT 166MHZ 86TSOP |
| IS42S32400B-7B | 制造商:Integrated Silicon Solution Inc 功能描述:IC SDRAM 128MBIT 143MHZ 90FBGA |
| IS42S32400B-7BI | 制造商:Integrated Silicon Solution Inc 功能描述:IC SDRAM 128MBIT 143MHZ 90FBGA |
| IS42S32400B-7BI-TR | 制造商:Integrated Silicon Solution Inc 功能描述:IC SDRAM 128MBIT 143MHZ 90FBGA |
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