參數(shù)資料
型號: IS43R16320A-6TL
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 32Meg x 16 512-MBIT DDR SDRAM
中文描述: 32M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: LEAD FREE, TSOP2-66
文件頁數(shù): 11/18頁
文件大?。?/td> 219K
代理商: IS43R16320A-6TL
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.
A
0
3/22/06
11
ISSI
IS43R16320A
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, I
DD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to V
SS
.
2. Tests for AC timing, I
DD
, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and I
DD
tests may use a V
IL
to V
IH
swing of up to 1.5V in the test environment, but input timing is still referenced
to V
REF
(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between V
IL(AC)
and
V
IH(AC)
.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a
result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input low (high) level.
AC Output Load Circuit Diagrams
50
Timing Reference Point
Output
(V
OUT
)
30pF
V
TT
相關(guān)PDF資料
PDF描述
IS43R16800A-6 8Meg x 16 128-MBIT DDR SDRAM
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