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參數(shù)資料
| 型號(hào)： | IS43R32400A-6BLI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 4Meg x 32 128-MBIT DDR SDRAM |
| 中文描述： | 4M X 32 DDR DRAM, 0.7 ns, PBGA144 |
| 封裝： | 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MINI, FBGA-144 |
| 文件頁數(shù)： | 18/25頁 |
| 文件大小： | 1295K |
| 代理商： | IS43R32400A-6BLI |
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00D
02/15/06
ISSI
IS43R32400A
Auto Refresh
The DDR SDRAM is issued the Auto Refresh com-
mand during normal operation to maintain data in the
memory array. All the banks must be idle for the
command to be executed. The device has 4096
refresh cycles every 32ms.
Self Refresh
To issue the Self Refresh command, CKE must be
Low. When the DDR SDRAM is in Self Refresh mode,
it retains the data contents without external clocking,
and ignores other input signals. The DLL is disabled
upon entering the Self Refresh mode, and is enabled
again upon leaving the mode. To exit Self Refresh, all
inputs must be stable prior to CKE going High. Next,
a NOP command command must be issued on each
clock cycle for at least tXSNR to ensure that internal
refresh operations are completed. To prepare for a
memory access, the DDR SDRAM must receive a DLL
reset followed by a NOP command for 200 clock
cycles.
DEVICE OPERATION
Bank and Row Activation
An Active command must be issued to the DDR
SDRAM to open a bank and row prior to an access.
The row will be available for a Read or Write com-
mand once a time tRCD has occurred. The Active
command is depicted in the figure. As CLK goes
High,
CS
and
RAS
are Low, while CKE,
WE
, and
CAS
are High. Upon issuing the Active command, the
values on the address inputs specify the row, and BA0
and BA1 specify the bank. When an Active command
is issued for a bank and row, another row in that same
bank may be activated after a time tRC. When an
Active command is issued for a bank and row, a row in
a different bank may be activated after a time tRRD.
(Note: to ensure that time requirement tRCD, tRC, or
tRRD is met, NOP commands should be issued for a
whole number of clock cycles that is greater than the
time requirement (ie. tRCD) divided by the clock
period.)
Read Operation
A Read command starts a burst from an activated row.
The Read command is depicted in the figure. As CLK
goes High,
CS
and
CAS
are Low, while
RAS
, CKE,
and
WE
are High. The values on the inputs BA0 and
BA1 specify the bank to access, and the address
inputs specify the starting column in the open row. If
Auto Pre-charge is enabled in the Read command, the
open row will be pre-charged after completion of the
Read burst. Unless stated otherwise, all timing dia-
grams for Read operations have disabled Auto Pre-
charge.
The Read command causes data to be retrieved and
placed in the pipeline. The subsequent command can
be NOP, Read, or Terminate Burst. The data from the
starting column specified in the Read command
appears on I/O pins following a CAS latency of after
the Read command. On each CLK and
CLK
crossing,
the data from the next column in the burst sequence is
output from the pipeline until the burst is completed
(see Read Burst, Non-consecutive Read Burst, and
Consecutive Read Burst). There are two cases in
which a full Read burst length is not completed. The
first is when the data retrieved from a subsequent
Read burst interrupts the previous burst (see Random
Read Accesses). The second is when a subsequent
Burst Terminate command truncates the burst (see
Terminating a Read Burst and Read to Write). The
Burst Terminate and Read commands obey the same
CAS latency timing such that they should be issued x
cycles after a previous Read command, where x is the
number of pairs of columns to output. By following a
desired command sequence, continuous data can be
output with either whole Read bursts or truncated
Read bursts. Whenever a Read burst finishes and no
other commands have been initiated, the I/O returns to
High-Z.
If Auto Pre-charge is not enabled in the Read burst,
the Pre-charge command can be issued separately
following the Read command. The Pre-charge com-
mand should be received by the device x cycles after
the Read command, where x is the desired number of
pairs of columns to output during the Read burst.
After the Pre-charge command, it is necessary to wait
until both tRAS and tRP have been met before issuing
a new command to the same bank.
Data Strobe output is driven synchronously with the
output data on the I/O pins. The Low portion of the
Data Strobe just prior to the first output data is the
Read Pre-amble; and the Low portion coinciding with
the last output data is the Read Post-amble. Before
any Write command can be executed, any previous
Read burst must have been completed normally or
truncated by a Burst Terminate command. In the
diagram Read to Write, a Burst Terminate command is
issued to truncate a Read Burst early, and begin a
Write operation. After the Write command, a time
tDQSS is required prior to latching the data on the I/O.
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| IS43R32400A-6BL-TR | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 4Mx32 333MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R32400A-6B-TR | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 4Mx32 333MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R32400D-4BL | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M (4Mx32) 250MHz DDR 2.5v RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R32400D-4BL-TR | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M (4Mx32) 250MHz DDR 2.5v RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R32400D-4B-TR | 制造商:Integrated Silicon Solution Inc 功能描述: |
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