參數(shù)資料
型號: IS45LV44002B-50JA1
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
中文描述: 4M X 4 EDO DRAM, 50 ns, PDSO24
封裝: 0.300 INCH, PLASTIC, SOJ-24
文件頁數(shù): 6/20頁
文件大小: 137K
代理商: IS45LV44002B-50JA1
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
09/12/05
IS45LV44002B
ISSI
AC CHARACTERISTICS
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
Symbol
t
RC
t
RAC
t
CAC
t
AA
t
RAS
t
RP
t
CAS
t
CP
t
CSH
t
RCD
t
ASR
t
RAH
t
ASC
t
CAH
t
AR
Parameter
Random READ or WRITE Cycle Time
Access Time from
RAS
(6, 7)
Access Time from
CAS
(6, 8, 15)
Access Time from Column-Address
(6)
RAS
Pulse Width
RAS
Precharge Time
CAS
Pulse Width
(23)
CAS
Precharge Time
(9)
CAS
Hold Time
(21)
RAS
to
CAS
Delay Time
(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time
(20)
Column-Address Hold Time
(20)
Column-Address Hold Time
(referenced to
RAS
)
RAS
to Column-Address Delay Time
(11)
Column-Address to
RAS
Lead Time
RAS
to
CAS
Precharge Time
RAS
Hold Time
RAS
Hold Time from
CAS
Precharge
CAS
to Output in Low-Z
(15, 24)
CAS
to
RAS
Precharge Time
(21)
Output Disable Time
(19, 24)
Output Enable Time
(15, 16)
Output Enable Data Delay (Write)
OE
HIGH Hold Time from
CAS
HIGH
OE
HIGH Pulse Width
OE
LOW to
CAS
HIGH Setup Time
Read Command Setup Time
(17, 20)
Read Command Hold Time
(referenced to
RAS
)
(12)
Read Command Hold Time
(referenced to
CAS
)
(12, 17, 21)
Write Command Hold Time
(17)
Write Command Hold Time
(referenced to
RAS
)
(17)
Write Command Pulse Width
(17)
WE
Pulse Widths to Disable Outputs
Min.
84
50
30
8
9
38
12
0
8
0
8
30
Max.
50
13
25
10K
10K
37
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RAD
t
RAL
t
RPC
t
RSH
t
RHCP
t
CLZ
t
CRP
t
OD
t
OE
t
OED
t
OEHC
t
OEP
t
OES
t
RCS
t
RRH
10
25
5
8
30
0
5
3
12
5
10
5
0
0
25
15
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RCH
0
ns
t
WCH
t
WCR
8
40
ns
ns
t
WP
t
WPZ
8
7
ns
ns
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