參數(shù)資料
型號: IS45S32400B
廠商: Integrated Silicon Solution, Inc.
英文描述: 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
中文描述: 4Meg × 32 128兆位同步DRAM
文件頁數(shù): 12/60頁
文件大?。?/td> 642K
代理商: IS45S32400B
ISSI
12
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
07/10/06
IS45S32400B
CKE RELATED COMMAND TRUTH TABLE
(1)
CKE
n-1
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
Current State
Self-Refresh (S.R.)
Operation
INVALID, CLK (n - 1) would exit S.R.
Self-Refresh Recovery
(2)
Self-Refresh Recovery
(2)
Illegal
Illegal
Maintain S.R.
Idle After t
RC
Idle After t
RC
Illegal
Illegal
Begin clock suspend next cycle
(5)
Begin clock suspend next cycle
(5)
Illegal
Illegal
Exit clock suspend next cycle
(2)
Maintain clock suspend
INVALID, CLK (n - 1) would exit P.D.
EXIT P.D. --> Idle
(2)
Maintain power down mode
Refer to operations n Operative Command Table
Refer to operations n Operative Command Table
Refer to operations n Operative Command Table
Auto-Refresh
Refer to operations n Operative Command Table
Refer to operations n Operative Command Table
Refer to operations n Operative Command Table
Refer to operations n Operative Command Table
Self-Refresh
(3)
Refer to operations n Operative Command Table
Power-Down
(3)
Refer to operations n Operative Command Table
Begin clock suspend next cycle
(4)
Exit clock suspend next cycle
Maintain clock suspend
n
X
H
H
H
H
L
H
H
H
H
L
L
L
L
H
L
X
H
L
H
H
H
H
H
L
L
L
L
L
X
H
L
H
L
CS
X
H
L
L
L
X
H
L
L
L
H
L
L
L
X
X
X
X
X
H
L
L
L
L
H
L
L
L
L
X
X
X
X
X
RAS
X
X
H
H
L
X
X
H
H
L
X
H
H
L
X
X
X
X
X
X
H
L
L
L
X
H
L
L
L
X
X
X
X
X
CAS
X
X
H
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
H
L
L
X
X
H
L
L
X
X
X
X
X
WE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
H
L
X
X
X
X
X
Address
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Op - Code
X
Op - Code
X
X
X
X
X
Self-Refresh Recovery
Power-Down (P.D.)
Both Banks Idle
Any state
other than
listed above
Notes:
1. H : High level, L : low level, X : High or low level (Don’t care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum
setup time must be satisfied
before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if t
XSR
is not satisfied.
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