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參數(shù)資料
| 型號： | IS61C1024-12HI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | RES POWER .020 OHM 2W 5% SMT |
| 中文描述： | 128K X 8 STANDARD SRAM, 12 ns, PDSO32 |
| 封裝： | 8 X 13.40 MM, STSOP1-32 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 80K |
| 代理商： | IS61C1024-12HI |
IS61C1024
IS61C1024L
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR028-1J
11/03/98
ISSI
WRITE CYCLE NO. 2
(
OE
is HIGH During Write Cycle)
(1,2)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
HIGH
CE2
CE2_WR2.eps
Notes:
1. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE1
t
SCE2
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
CE2
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
CE2_WR1.eps
AC WAVEFORMS
WRITE CYCLE NO. 1
(
CE
Controlled,
OE
is HIGH or LOW)
(1 )
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61C1024-12J | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C1024-12JI | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C1024-12K | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C1024-12KI | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C1024-12T | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61C1024-12J | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C1024-12JI | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Async Single 5V 1M-Bit 128K x 8 12ns 32-Pin SOJ |
| IS61C1024-12JR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| IS61C1024-12JRI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| IS61C1024-12K | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:128K x 8 HIGH-SPEED CMOS STATIC RAM |
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