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參數(shù)資料
| 型號(hào)： | IS61C64AH |
| 英文描述： | 8K x 8 HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 8K的× 8高速CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 433K |
| 代理商： | IS61C64AH |
IS61C64AH
Integrated Circuit Solution Inc.
7
SR001-B
1
2
3
4
5
6
7
8
9
10
11
12
AC WAVEFORMS
WRITE CYCLE NO. 2
(
OE
is HIGH During Write Cycle)
(1,2)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
HIGH
CE2
WRITE CYCLE NO. 3
(
OE
is LOW During Write Cycle)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
HIGH
CE2
Notes:
1. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61C64AH-15J | 8K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C64AH-15U | 8K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C64AH-20J | 8K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C64AH-20U | 8K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C64AH-25J | 8K x 8 HIGH-SPEED CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61C64AH-12J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| IS61C64AH-12N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| IS61C64AH-15J | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:8K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C64AH-15N | 制造商:Integrated Silicon Solution Inc 功能描述:Static RAM, 8Kx8, 28 Pin, Plastic, DIP 制造商:ISSI/93-94 功能描述:Static RAM, 8Kx8, 28 Pin, Plastic, DIP |
| IS61C64AH-15U | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:8K x 8 HIGH-SPEED CMOS STATIC RAM |
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