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參數(shù)資料
| 型號： | IS61LF102418A |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| 中文描述： | 256 × 72，為512k × 36，1024K × 18 35.7同步流動，通過靜態(tài)內(nèi)存 |
| 文件頁數(shù)： | 23/35頁 |
| 文件大?。?/td> | 281K |
| 代理商： | IS61LF102418A |
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
04/21/06
23
ISSI
IS61LF25672A IS61LF51236A IS61LF102418A
IS61VF25672A IS61VF51236A IS61VF102418A
TAP INSTRUCTION SET
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as
RESERVED
and should not be used and the other five instructions are
described below. The TAP controller used in this SRAM is
not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
The TAP controller cannot be used to load address, data or
control signals and cannot preload the
Input
or
Output
buffers. The
SRAM
does not implement the
1149.1
com-
mands
EXTEST
or
INTEST
or the
PRELOAD
portion of
SAMPLE/PRELOAD
; instead it performs a capture of the
Inputs and Output
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed be-
tween TDI and TDO. During this state, instructions are
shifted from the instruction register through the TDI and
TDO pins. To execute an instruction once it is shifted in,
the TAP controller must be moved into the Update-IR
state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
The TAP controller recognizes an all-0 instruction. When
an EXTEST instruction is loaded into the instruction regis-
ter, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is a difference between
the instructions, unlike the
SAMPLE/PRELOAD
instruction,
EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit
code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.
SAMPLE-Z
The SAMPLE-Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also
places all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction.
The PRELOAD portion of this instruction is not imple-
mented, so the TAP controller is not fully 1149.1 compli-
ant. When the SAMPLE/PRELOAD instruction is loaded
to the instruction register and the TAP controller is in the
Capture-DR state, a snapshot of data on the inputs and
output pins is captured in the boundary scan register.
It is important to realize that the TAP controller clock
operates at a frequency up to 10 MHz, while the SRAM
clock runs more than an order of magnitude faster. Be-
cause of the clock frequency differences, it is possible that
during the Capture-DR state, an input or output will under-
go a transition. The TAP may attempt a signal capture
while in transition (metastable state). The device will not
be harmed, but there is no guarantee of the value that will
be captured or repeatable results.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be stabi-
lized long enough to meet the TAP controller’s capture set-
up plus hold times (t
CS
and t
CH
). To insure that the SRAM
clock input is captured correctly, designs need a way to
stop (or slow) the clock during a SAMPLE/PRELOAD
instruction. If this is not an issue, it is possible to capture
all other signals and simply ignore the value of the CLK and
CLK
captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the
PRELOAD
part of the command is not
implemented, putting the
TAP
into the
Update
to the
Update-DR
state while performing a
SAMPLE/PRELOAD
instruction will
have the same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the
bypass register is placed between the TDI and TDO pins.
The advantage of the BYPASS instruction is that it short-
ens the boundary scan path when multiple devices are
connected together on a board.
RESERVED
These instructions are not implemented but are reserved
for future use. Do not use these instructions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61LF102418A-6.5B2 | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61LF102418A-6.5B2I | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61LF102418A-6.5B3 | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61LF102418A-6.5B3I | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61LF102418A-6.5TQ | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61LF102418A-6.5B2 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61LF102418A-6.5B2I | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61LF102418A-6.5B3 | 功能描述:靜態(tài)隨機存取存儲器 18Mb,Flow-Through,Sync,1Mb x 18,6.5ns,3.3v or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61LF102418A-6.5B3I | 功能描述:靜態(tài)隨機存取存儲器 18Mb,Flow-Through,Sync,1Mb x 18,6.5ns,3.3v or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61LF102418A-6.5B3I-TR | 功能描述:靜態(tài)隨機存取存儲器 18Mb,Flow-Through,Sync,1Mb x 18,6.5ns,3.3v or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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