參數(shù)資料
型號: IS61LPD102418A-200TQI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
中文描述: 1M X 18 CACHE SRAM, 3.1 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 9/29頁
文件大小: 219K
代理商: IS61LPD102418A-200TQI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/03/06
9
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A, IS61LPD102418A
ISSI
PARTIAL TRUTH TABLE
Function
GW
BWE
BWa
BWb
BWc
BWd
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
H
H
H
H
L
H
L
L
L
X
X
H
L
L
X
X
H
H
L
X
X
H
H
L
X
X
H
H
L
X
TRUTH TABLE
(1-8)
(1CE option)
NEXT CYCLE
ADDRESS
CE
ADSP
ADSC
ADV
WRITE
OE
DQ
Deselected
None
H
X
L
X
X
X
High-Z
Read, Begin Burst
External
L
L
X
X
X
L
Q
Read, Begin Burst
External
L
L
X
X
X
H
High-Z
Write, Begin Burst
External
L
H
L
X
L
X
D
Read, Begin Burst
External
L
H
L
X
H
L
Q
Read, Begin Burst
External
L
H
L
X
H
H
High-Z
Read, Continue Burst
Next
X
H
H
L
H
L
Q
Read, Continue Burst
Next
X
H
H
L
H
H
High-Z
Read, Continue Burst
Next
H
X
H
L
H
L
Q
Read, Continue Burst
Next
H
X
H
L
H
H
High-Z
Write, Continue Burst
Next
X
H
H
L
L
X
D
Write, Continue Burst
Next
H
X
H
L
L
X
D
Read, Suspend Burst
Current
X
H
H
H
H
L
Q
Read, Suspend Burst
Current
X
H
H
H
H
H
High-Z
Read, Suspend Burst
Current
H
X
H
H
H
L
Q
Read, Suspend Burst
Current
H
X
H
H
H
H
High-Z
Write, Suspend Burst
Current
X
H
H
H
L
X
D
Write, Suspend Burst
Current
H
X
H
H
L
X
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For
WRITE
, L means one or more byte write enable signals (
BWa
,
BWb
,
BWc
or
BWd
) and
BWE
are LOW or
GW
is LOW.
WRITE
= H for all
BWx
,
BWE
,
GW
HIGH.
3.
BWa
enables WRITEs to DQa’s and DQPa.
BWb
enables WRITEs to DQb’s and DQPb.
BWc
enables WRITEs to DQc’s and
DQPc.
BWd
enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and
DQPd are only available on the x36 version.
4. All inputs except
OE
and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation,
OE
must be HIGH before the input data setup time and held HIGH during the
input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.
ADSP
LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
相關PDF資料
PDF描述
IS61LPD102418A-250B3 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
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IS61LPD102418A-250B3 功能描述:靜態(tài)隨機存取存儲器 18Mb,Pipeline,Sync,1Mb x 18,250MHz,3.3V or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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IS61LPD102418A-250B3I-TR 功能描述:靜態(tài)隨機存取存儲器 18Mb,Pipeline,Sync,1Mb x 18,250MHz,3.3V or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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