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| 型號(hào)： | IS61LPD51218A-200B2 |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| 中文描述： | 512K X 18 CACHE SRAM, 3.1 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1MM PITCH, PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 23/32頁(yè) |
| 文件大?。?/td> | 216K |
| 代理商： | IS61LPD51218A-200B2 |
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/09/05
23
IS61VPD25636A, IS61VPD51218A, IS61LPD25636A, IS61LPD51218A
ISSI
TAP Electrical Characteristics
Over the Operating Range
(1,2)
Symbol
Parameter
Test Conditions
Min.
Max.
Units
V
OH1
Output HIGH Voltage
I
OH
= –2.0 mA
1.7
—
V
V
OH2
Output HIGH Voltage
I
OH
= –100 μA
2.1
—
V
V
OL1
Output LOW Voltage
I
OL
= 2.0 mA
—
0.7
V
V
OL2
Output LOW Voltage
I
OL
= 100 μA
—
0.2
V
V
IH
Input HIGH Voltage
1.7
V
DD
+0.3
V
V
IL
Input LOW Voltage
–0.3
0.7
V
I
X
Input Load Current
Vss
≤
V I
≤
V
DDQ
–5
5
mA
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: V
IH
(AC)
≤
V
DD
+1.5V for t
≤
t
TCYC
/2,
Undershoot:V
IL
(AC)
≤
0.5V for t
≤
t
TCYC
/2,
Power-up: V
IH
< 2.6V and V
DD
< 2.4V and V
DDQ
< 1.4V for t < 200 ms.
TAP AC ELECTRICAL CHARACTERISTICS
(1,2)
(OVER OPERATING RANGE)
Symbol
Parameter
Min.
Max.
Unit
t
TCYC
TCK Clock cycle time
100
—
ns
f
TF
TCK Clock frequency
—
10
MHz
t
TH
TCK Clock HIGH
40
—
ns
t
TL
TCK Clock LOW
40
—
ns
t
TMSS
TMS setup to TCK Clock Rise
10
—
ns
t
TDIS
TDI setup to TCK Clock Rise
10
—
ns
t
CS
Capture setup to TCK Rise
10
—
ns
t
TMSH
TMS hold after TCK Clock Rise
10
—
ns
t
TDIH
TDI Hold after Clock Rise
10
—
ns
t
CH
Capture hold after Clock Rise
10
—
ns
t
TDOV
TCK LOW to TDO valid
—
20
ns
t
TDOX
TCK LOW to TDO invalid
0
—
ns
Notes:
1. Both t
CS
and t
CH
refer to the set-up and hold time latching data requirements from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1 ns.
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| IS61LPD51218A-200B2I | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-200B3 | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-200B3I | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-200TQ | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-200TQI | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61LPD51218A-200B2I | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-200B3 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-200B3I | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-200TQ | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-200TQI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
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