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參數(shù)資料
| 型號： | IS61LPD51218A-200B3 |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| 中文描述： | 512K X 18 CACHE SRAM, 3.1 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 216K |
| 代理商： | IS61LPD51218A-200B3 |
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/09/05
15
IS61VPD25636A, IS61VPD51218A, IS61LPD25636A, IS61LPD51218A
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-250
Min.
-200
Min.
Symbol
Parameter
Max.
Max.
Unit
f
MAX
Clock Frequency
—
250
—
200
MHz
t
KC
Cycle Time
4.0
—
5
—
ns
t
KH
Clock High Time
1.7
—
2
—
ns
t
KL
Clock Low Time
1.7
—
2
—
ns
t
KQ
Clock Access Time
—
2.6
—
3.1
ns
t
KQX
(2)
Clock High to Output Invalid
0.8
—
1.5
—
ns
t
KQLZ
(2,3)
Clock High to Output Low-Z
0.8
—
1
—
ns
t
KQHZ
(2,3)
Clock High to Output High-Z
—
2.6
—
3.0
ns
t
OEQ
Output Enable to Output Valid
—
2.6
—
3.1
ns
t
OELZ
(2,3)
Output Enable to Output Low-Z
0
—
0
—
ns
t
OEHZ
(2,3)
Output Disable to Output High-Z
—
2.6
—
3.0
ns
t
AS
Address Setup Time
1.2
—
1.4
—
ns
t
WS
Read/Write Setup Time
1.2
—
1.4
—
ns
t
CES
Chip Enable Setup Time
1.2
—
1.4
—
ns
t
AVS
Address Advance Setup Time
1.2
—
1.4
—
ns
t
DS
Data Setup Time
1.2
—
1.4
—
ns
t
AH
Address Hold Time
0.3
—
0.4
—
ns
t
WH
Write Hold Time
0.3
—
0.4
—
ns
t
CEH
Chip Enable Hold Time
0.3
—
0.4
—
ns
t
AVH
Address Advance Hold Time
0.3
—
0.4
—
ns
t
DH
Data Hold Time
0.3
—
0.4
—
ns
t
PDS
ZZ High to Power Down
—
2
—
2
cyc
t
PUS
ZZ Low to Power Down
—
2
—
2
cyc
Note:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61LPD51218A-200B3I | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-200TQ | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-200TQI | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-250B2 | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-250B2I | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61LPD51218A-200B3I | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-200TQ | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-200TQI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-250B2 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218A-250B2I | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
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