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    參數(shù)資料
    

    


    


    
型號(hào)：
IS61LPS25636A-200TQ2I

    

    
廠商：
INTEGRATED SILICON SOLUTION INC

    

    
元件分類：
DRAM

    

    
英文描述：
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

    

    
中文描述：
256K X 36 CACHE SRAM, 3.1 ns, PQFP100

    

    
封裝：
TQFP-100

    

    
文件頁(yè)數(shù)：
20/32頁(yè)

    

    
文件大?。?/td>
217K

    

    
代理商：
IS61LPS25636A-200TQ2I


    

    

    

	
    
    
    

    
    
	
    20
    Integrated Silicon Solution, Inc. — 1-800-379-4774
    Rev. A
    04/29/05
    IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
    ISSI
    TEST DATA OUT (TDO)
    The TDO output pin is used to serially clock data-out from
    the registers. The output is active depending on the current
    state of the 
    TAP
     state machine (see 
    TAP
     Controller State
    Diagram). The output changes on the falling edge of TCK
    and TDO is connected to the Least Significant Bit (LSB) of
    any register.
    PERFORMING A TAP RESET
    A Reset is performed by forcing TMS HIGH (V
    DD
    ) for five
    rising edges of TCK. RESET may be performed while the
    SRAM is operating and does not affect its operation. At
    power-up, the TAP is internally reset to ensure that TDO
    comes up in a high-Z state.
    TAP REGISTERS
    Registers are connected between the TDI and TDO pins and
    allow data to be scanned into and out of the SRAM test
    circuitry
    . 
    Only one register can be selected at a time through
    the instruction registers. Data is serially loaded into the TDI
    pin on the rising edge of TCK and output on the TDO pin on
    the falling edge of TCK.
    Instruction Register
    Three-bit instructions can be serially loaded into the instruc-
    tion register. This register is loaded when it is placed
    between the 
    TDI
     and 
    TDO
     pins. (See 
    TAP
     Controller Block
    Diagram) At power-up, the instruction register is loaded
    with the IDCODE instruction. It is also loaded with the
    IDCODE instruction if the controller is placed in a reset state
    as previously described.
    When the TAP controller is in the CaptureIR state, the two
    least significant bits are loaded with a binary “01” pattern to
    allow for fault isolation of the board level serial test path.
    Bypass Register
    To save time when serially shifting data through registers,
    it is sometimes advantageous to skip certain states. The
    bypass register is a single-bit register that can be placed
    between TDI and TDO pins. This allows data to be shifted
    through the 
    SRAM
     with minimal delay. The bypass register
    is set LOW (V
    SS
    ) when the BYPASS instruction is ex-
    ecuted.
    Boundary Scan Register
    The boundary scan register is connected to all input and
    output pins on the 
    SRAM
    . Several no connect 
    (NC)
     pins are
    also included in the scan register to reserve pins for higher
    density devices. The x36 configuration has a 75-bit-long
    register and the x18 configuration also has a 75-bit-long
    register. The boundary scan register is loaded with the
    contents of the RAM Input and Output ring when the TAP
    controller is in the Capture-DR state and then placed
    between the 
    TDI
     and 
    TDO
     pins when the controller is moved
    to the 
    Shift-DR
     state. The EXTEST, SAMPLE/PRELOAD
    and SAMPLE-Z instructions can be used to capture the
    contents of the Input and Output ring.
    The Boundary Scan Order tables show the order in which the
    bits are connected. Each bit corresponds to one of the
    bumps on the SRAM package. The MSB of the register is
    connected to TDI, and the LSB is connected to TDO.
    Identification (ID) Register
    The ID register is loaded with a vendor-specific, 32-bit code
    during the Capture-DR state when the IDCODE command is
    loaded to the instruction register. The IDCODE is hardwired
    into the SRAM and can be shifted out when the TAP
    controller is in the Shift-DR state. The ID register has vendor
    code and other information described in the Identification
    Register Definitions table.
    Scan Register Sizes
    Register
    Name
    Bit Size
    (x18)
    Bit Size
    (x36)
    Instruction
    3
    3
    Bypass
    1
    1
    ID
    32
    32
    Boundary Scan
    75
    75
    IDENTIFICATION REGISTER DEFINITIONS
    Instruction Field
    Description
    256K x 36
    512K x 18
    Revision Number (31:28)
    Reserved for version number.
    xxxx
    xxxx
    Device Depth (27:23)
    Defines depth of SRAM. 256K or 512K
    00111
    01000
    Device Width (22:18)
    Defines width of the SRAM. x36 or x18
    00100
    00011
    ISSI Device ID (17:12)
    Reserved for future use.
    xxxxx
    xxxxx
    ISSI JEDEC ID (11:1)
    Allows unique dentification of SRAM vendor.
    00011010101
    00011010101
    ID Register Presence (0)
    Indicate the presence of an ID register.
    1
    1
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
IS61LPS25636A-200TQI
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

    

    
IS61LPS25636A-200TQLI
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

    

    
IS61LPS25636A-250B2
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

    

    
IS61LPS25636A-250B2I
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

    

    
IS61LPS25636A-250B3
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
IS61LPS25636A-200TQ2I-TR
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8Mb 256Kx36 200Mhz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
IS61LPS25636A-200TQ2LI
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M (256Kx36) 200MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
IS61LPS25636A-200TQ2LI-TR
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M (256Kx36) 200MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
IS61LPS25636A-200TQI
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8Mb 256Kx36 200Mhz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
IS61LPS25636A-200TQI-TR
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8Mb 256Kx36 200Mhz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
    
    
    
	
    	
    
    
     
     
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