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參數(shù)資料
| 型號(hào)： | IS61LV 216L |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 32K x 17 Low Voltage High-Speed CMOS Static RAM(3.3V,32K x 16 低壓高速CMOS靜態(tài)RAM) |
| 中文描述： | 32K的低電壓× 17高速CMOS靜態(tài)RAM（3.3伏，32K的× 16低壓高速的CMOS靜態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 102K |
| 代理商： | IS61LV 216L |
IS61LV3216L
ISSI
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-10
-12
-15
-20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
WC
Write Cycle Time
10
—
12
—
15
—
20
—
ns
t
SCE
CE
to Write End
8
—
9
—
10
—
12
—
ns
t
AW
Address Setup Time
to Write End
9
—
10
—
10
—
12
—
ns
t
HA
Address Hold from Write End
1
—
1
—
1
—
1
—
ns
t
SA
Address Setup Time
0
—
0
—
0
—
0
—
ns
t
PWB
LB
,
UB
Valid to End of Write
9
—
10
—
11
—
12
—
ns
t
PWE
WE
Pulse Width
7
—
8
—
10
—
11
—
ns
t
SD
Data Setup to Write End
5
—
6
—
7
—
—
8
ns
t
HD
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
t
HZWE
(2)
WE
LOW to High-Z Output
—
5
—
6
—
7
—
8
ns
t
LZWE
(2)
WE
HIGH to Low-Z Output
1
—
1
—
1
—
1
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
3. The internal write time is defined by the overlap of
CE
LOW and
UB
or
LB
, and
WE
LOW. All signals must be
in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
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