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參數資料
| 型號： | IS61LV10248-8TI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 8 HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 1M X 8 STANDARD SRAM, 8 ns, PDSO44 |
| 封裝： | PLASTIC, TSOP2-44 |
| 文件頁數： | 8/16頁 |
| 文件大?。?/td> | 123K |
| 代理商： | IS61LV10248-8TI |
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
04/13/06
IS61LV10248
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-8
-10
Symbol
t
WC
t
SCE
t
AW
Parameter
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
8
—
10
—
ns
CE
to Write End
6.5
—
8
—
ns
Address Setup Time
to Write End
6.5
—
8
—
ns
t
HA
t
SA
t
PWE
1
t
PWE
2
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
WE
Pulse Width
6.5
—
8
—
ns
WE
Pulse Width (
OE
= LOW)
8
—
10
—
ns
Data Setup to Write End
5
—
6
—
ns
Data Hold from Write End
0
—
0
—
ns
WE
LOW to High-Z Output
—
3.5
—
5
ns
WE
HIGH to Low-Z Output
2
—
2
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
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