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參數(shù)資料
| 型號： | IS61LV6432 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64K x 32 Synchronous Pipelined SRAM(64K x 32 同步流水線靜態(tài)RAM) |
| 中文描述： | 64K的同步流水線× 32的SRAM（64K的× 32同步流水線靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 174K |
| 代理商： | IS61LV6432 |
IS61LV6432
4
Integrated Silicon Solution, Inc.
PRELIMINARY
SR018-1C
06/01/98
ISSI
TRUTH TABLE
Address
Used
Operation
CE1
CE2
CE3
ADSP
ADSC
ADV
WRITE
OE
DQ
Deselected, Power-down
None
H
X
X
X
L
X
X
X
High-Z
Deselected, Power-down
None
L
L
X
L
X
X
X
X
High-Z
Deselected, Power-down
None
L
X
H
L
X
X
X
X
High-Z
Deselected, Power-down
None
L
L
X
H
L
X
X
X
High-Z
Deselected, Power-down
None
L
X
H
H
L
X
X
X
High-Z
Read Cycle, Begin Burst External
Read Cycle, Begin Burst External
Write Cycle, Begin Burst External
Read Cycle, Begin Burst External
Read Cycle, Begin Burst External
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst Current
Read Cycle, Suspend Burst Current
Read Cycle, Suspend Burst Current
Read Cycle, Suspend Burst Current
Write Cycle, Suspend Burst Current
Write Cycle, Suspend Burst Current
L
L
L
L
L
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Next
Next
Next
Next
Next
Next
X
X
H
H
X
H
X
X
H
H
X
H
Notes:
1. All inputs except
OE
must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care.
WRITE
=L means any one or more byte write enable signals (
BW
1-
BW
4) and
BWE
are LOW or
GW
is LOW.
WRITE
=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation,
OE
must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5.
ADSP
LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
Function
GW
BWE
BW1
BW2
BW3
BW4
READ
READ
WRITE Byte 1
WRITE All Bytes
WRITE All Bytes
H
H
H
X
L
H
X
L
L
X
X
H
L
L
X
X
H
H
L
X
X
H
H
L
X
X
H
H
L
X
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61LV6432-117PQ | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-117PQI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-117TQ | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-117TQI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-133PQ | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
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