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參數(shù)資料
| 型號： | IS61LV6464 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64K x 64 Synchronous Pipelined SRAM(64K x 64 同步流水線靜態(tài)RAM) |
| 中文描述： | 64K的同步流水線× 64的SRAM（64K的× 64同步流水線靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 4/17頁 |
| 文件大小： | 223K |
| 代理商： | IS61LV6464 |
ISSI
IS61LV6464
4
Integrated Silicon Solution, Inc.
PRELIMINARY
SR023-0D
06/01/98
TRUTH TABLE
ADDRESS
USED
OPERATION
CE3
CE2
CE3
CE2
CE
ADSP ADSC
ADV WRITE
OE
CLK
I/O
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
None
None
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
X
L
X
X
X
L
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
X
L
L
L
L
H
H
H
H
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
X
X
L
L
L
L
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
X
X
X
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
Din
Dout
High-Z
Dout
High-Z
Dout
High-Z
Din
Din
Dout
High-Z
Dout
High-Z
Din
Din
Notes:
1. All inputs except
OE
must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care.
WRITE
=L means any one or more byte write enable signals (
BW
1-
BW
8) and
BWE
are LOW or
GW
is LOW.
WRITE
=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation,
OE
must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5.
ADSP
LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of clock.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IS61LV6464-100PQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 Fast Synchronous SRAM |
| IS61LV6464-100TQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64K x 64 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6464-6PQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64K x 64 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6464-6PQI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 Fast Synchronous SRAM |
| IS61LV6464-6TQ | 制造商:Integrated Silicon Solution Inc 功能描述: |
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