參數(shù)資料
型號: IS61NLP25618-133B
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: PIPELINE NO WAIT STATE BUS SRAM
中文描述: 256K X 18 ZBT SRAM, 4.2 ns, PBGA119
封裝: PLASTIC, BGA-119
文件頁數(shù): 6/20頁
文件大小: 154K
代理商: IS61NLP25618-133B
6
Integrated Silicon Solution, Inc.
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00C
11/30/00
IS61NP12832
IS61NLP12832
IS61NP12836
IS61NLP12836
IS61NP25618
IS61NLP25618
ISSI
SYNCHRONOUS TRUTH TABLE
(1)
Address
Used
Operation
CS
1
CS2
CS
2
ADV
WE
BW
x
OE
CKE
CLK
Not Selected Continue
Begin Burst Read
Continue Burst Read
NOP/Dummy Read
Dummy Read
Begin Burst Write
Continue Burst Write
NOP/Write Abort
Write Abort
Ignore Clock
N/A
X
L
X
L
X
L
X
L
X
X
X
H
X
H
X
H
X
H
X
X
X
L
X
L
X
L
X
L
X
X
H
L
H
L
H
L
H
L
H
X
X
H
X
H
X
L
X
L
X
X
X
X
X
X
X
L
L
H
H
X
X
L
L
H
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
H
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
Next Address
Current Address
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4.
WE
= L means Write operation in Write Truth Table.
WE
= H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and
OE
).
BURST
READ
DESELECT
BURST
WRITE
BEGIN
READ
BEGIN
WRITE
READ
WRITE
READ
WRITE
BURST
BURST
BURST
DS
DS
DS
READ
DS
DS
READ
WRITE
WRITE
BURST
BURST
WRITE
READ
STATE DIAGRAM
相關PDF資料
PDF描述
IS61NLP25618-133TQ PIPELINE NO WAIT STATE BUS SRAM
IS61NLP25618-5B PIPELINE NO WAIT STATE BUS SRAM
IS61NLP25618-5TQ PIPELINE NO WAIT STATE BUS SRAM
IS61NLP25618-5TQI PIPELINE NO WAIT STATE BUS SRAM
IS61NP12832 PIPELINE NO WAIT STATE BUS SRAM
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