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參數(shù)資料
| 型號： | IS62C1024AL-35TI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 8 LOW POWER CMOS STATIC RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 35 ns, PDSO32 |
| 封裝： | 20 X 8 MM, TSOP1-32 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 423K |
| 代理商： | IS62C1024AL-35TI |
6
Integrated Circuit Solution Inc.
SR016-0B
IS62C1024
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range, Standard and Low
Power)
-35
-45
-55
-70
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
WC
Write Cycle Time
35
—
45
—
55
—
70
—
ns
t
SCE
1
CE1
to Write End
25
—
35
—
50
—
60
—
ns
t
SCE
2
CE2 to Write End
25
—
35
—
50
—
60
—
ns
t
AW
Address Setup Time to Write End
25
—
35
—
45
—
60
—
ns
t
HA
Address Hold from Write End
0
—
0
—
0
—
0
—
ns
t
SA
Address Setup Time
0
—
0
—
0
—
0
—
ns
t
PWE
(4)
WE
Pulse Width
25
—
35
—
40
—
50
—
ns
t
SD
Data Setup to Write End
20
—
25
—
25
—
30
—
ns
t
HD
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
t
HZWE
(2)
WE
LOW to High-Z Output
—
10
—
15
—
20
—
25
ns
t
LZWE
(2)
WE
HIGH to Low-Z Output
3
—
5
—
5
—
5
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with
OE
HIGH.
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
AC WAVEFORMS
WRITE CYCLE NO. 1 (
WE
Controlled)
(1,2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS62C1024AL-35TLI | 128K x 8 LOW POWER CMOS STATIC RAM |
| IS62C1024-45QI | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024-70QI | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024 | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024-35Q | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS62C1024AL-35TI-TR | 功能描述:靜態(tài)隨機(jī)存取存儲器 1Mb 128K x 8 35ns 5v Async 靜態(tài)隨機(jī)存取存儲器 5v RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS62C1024AL-35TLI | 功能描述:靜態(tài)隨機(jī)存取存儲器 1Mb 128K x 8 35ns 5v Async 靜態(tài)隨機(jī)存取存儲器 5v RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS62C1024AL-35TLI-TR | 功能描述:靜態(tài)隨機(jī)存取存儲器 1Mb 128K x 8 35ns 5v Async 靜態(tài)隨機(jī)存取存儲器 5v RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS62C1024AL-70QI | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS62C1024L | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:128K x 8 LOW POWER CMOS STATIC RAM |
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