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參數(shù)資料
| 型號(hào)： | IS62WV1288BLL-45QI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 45 ns, PDSO32 |
| 封裝： | 0.450 INCH, PLASTIC, SOP-32 |
| 文件頁(yè)數(shù)： | 8/15頁(yè) |
| 文件大?。?/td> | 111K |
| 代理商： | IS62WV1288BLL-45QI |
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Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
06/20/05
IS62WV1288ALL, IS62WV1288BLL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
45 ns
Min.
45
55 ns
Min.
55
70 ns
Symbol
t
WC
t
SCS1/
t
SCS2
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
(3)
t
LZWE
(3)
Parameter
Write Cycle Time
Max.
—
Max.
—
Min.
70
Max.
—
Unit
ns
CS1/
CS2 to Write End
Address Setup Time to Write End
35
35
—
—
45
45
—
—
60
60
—
—
ns
ns
Address Hold from Write End
Address Setup Time
0
0
—
—
0
0
—
—
0
0
—
—
ns
ns
WE
Pulse Width
Data Setup to Write End
35
20
—
—
40
25
—
—
50
30
—
—
ns
ns
Data Hold from Write End
WE
LOW to High-Z Output
0
—
—
20
0
—
—
20
0
—
—
20
ns
ns
WE
HIGH to Low-Z Output
5
—
5
—
5
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V
to V
DD
-0.2V/V
DD
-0.3V and output loading specified in Figure 1.
2.
The internal write time is defined by the overlap of
CS1
LOW, CS2 HIGH, and
WE
LOW. All signals must be in valid states to initiate a Write, but any one can go
inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (
CS1
/CS2 Controlled,
OE
= HIGH or LOW
)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
CS2
WE
DOUT
DIN
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS62WV1288ALL | 128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| IS62WV1288ALL-70BI | 128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| IS62WV1288ALL-70HI | 128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| IS62WV1288BLL | 128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| IS62WV1288BLL-45BI | 128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS62WV1288BLL-45TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| IS62WV1288BLL-45TLI | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS62WV1288BLL-55BI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| IS62WV1288BLL-55HI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mb 128Kx8 55ns Async 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS62WV1288BLL-55HI-TR | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mb 128Kx8 55ns Async 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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