參數(shù)資料
型號(hào): IS64WV1024BLL-15TLA3
廠商: INTEGRATED SILICON SOLUTION INC
元件分類(lèi): DRAM
英文描述: 128K x 8 HIGH-SPEED CMOS STATIC RAM
中文描述: 128K X 8 STANDARD SRAM, 15 ns, PDSO32
封裝: LEAD FREE, PLASTIC, TSOP2-32
文件頁(yè)數(shù): 10/17頁(yè)
文件大小: 135K
代理商: IS64WV1024BLL-15TLA3
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
05/10/06
ISSI
IS63WV1024BLL
IS64WV1024BLL
AC WAVEFORMS
WRITE CYCLE NO. 2
(1)
(
WE
Controlled,
OE
= HIGH during Write Cycle)
WRITE CYCLE NO. 3
(
WE
Controlled:
OE
is LOW During Write Cycle)
Notes:
1. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
> V
IH
.
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR2.eps
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
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