參數(shù)資料
型號: IS64WV12816BLL-15TLA3
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 128K x 16 HIGH-SPEED CMOS STATIC RAM
中文描述: 128K X 16 STANDARD SRAM, 15 ns, PDSO44
封裝: LEAD FREE, PLASTIC, TSOP2-44
文件頁數(shù): 8/15頁
文件大?。?/td> 126K
代理商: IS64WV12816BLL-15TLA3
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
02/03/06
ISSI
IS61WV12816BLL
IS64WV12816BLL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-12 ns
Min.
-15 ns
Min.
Symbol
t
WC
t
SCE
t
AW
Parameter
Max.
Max.
Unit
Write Cycle Time
12
15
ns
CE
to Write End
8
10
ns
Address Setup Time
to Write End
8
10
ns
t
HA
t
SA
t
PBW
t
PWE
1
t
PWE
2
t
SD
t
HD
t
HZWE
(3)
t
LZWE
(3)
Address Hold from Write End
0
0
ns
Address Setup Time
0
0
ns
LB
,
UB
Valid to End of Write
9
10
ns
WE
Pulse Width (
OE
= HIGH)
8
10
ns
WE
Pulse Width (
OE
= LOW)
10
12
ns
Data Setup to Write End
6
7
ns
Data Hold from Write End
0
0
ns
WE
LOW to High-Z Output
5
7
ns
WE
HIGH to Low-Z Output
0
0
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CE
LOW and
UB
or
LB
, and
WE
LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
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