參數(shù)資料
型號: IS65C256AL-25UA3
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 32K x 8 LOW POWER CMOS STATIC RAM
中文描述: 32K X 8 STANDARD SRAM, 25 ns, PDSO28
封裝: 0.330 INCH, PLASTIC, SOP-28
文件頁數(shù): 5/12頁
文件大小: 101K
代理商: IS65C256AL-25UA3
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
5
ISSI
IS65C256AL
IS62C256AL
Figure 1.
Figure 2.
480
Ω
5 pF
Including
jig and
scope
255
Ω
OUTPUT
5V
AC TEST LOADS
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-25 ns
Min.
-45 ns
Min.
Symbol
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCS
(2)
t
HZCS
(2)
t
PU
(3)
t
PD
(3)
Parameter
Max.
Max.
Unit
Read Cycle Time
25
45
ns
Address Access Time
25
45
ns
Output Hold Time
2
2
ns
CE
Access Time
25
45
ns
OE
Access Time
13
25
ns
OE
to Low-Z Output
0
0
ns
OE
to High-Z Output
0
12
0
20
ns
CE
to Low-Z Output
3
3
ns
CE
to High-Z Output
0
12
0
20
ns
CE
to Power-Up
0
0
ns
CE
to Power-Down
20
30
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
480
Ω
100 pF
Including
jig and
scope
255
Ω
OUTPUT
5V
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