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    參數(shù)資料
    型號: IS80C31-12PQ
    廠商: INTEGRATED SILICON SOLUTION INC
    元件分類: 微控制器/微處理器
    英文描述: CMOS SINGLE CHIP 8-BIT MICROCONTROLLER
    中文描述: 8-BIT, 12 MHz, MICROCONTROLLER, PQFP44
    封裝: PLASTIC, QFP-44
    文件頁數(shù): 29/43頁
    文件大?。?/td> 337K
    代理商: IS80C31-12PQ
    IS80C51
    IS80C31
    Integrated Silicon Solution, Inc. — 1-800-379-4774
    MC003-1D
    11/19/98
    29
    ISSI
    Table 9. Reset Values of the SFR's
    SFR Name
    PC
    ACC
    B
    PSW
    SP
    DPTR
    P0–P3
    IP
    IE
    TMOD
    TCON
    TH0
    TL0
    TH1
    TL1
    SCON
    SBUF
    PCON
    Reset Value
    0000H
    00H
    00H
    00H
    07H
    0000H
    FFH
    XXX00000B
    0XX00000B
    00H
    00H
    00H
    00H
    00H
    00H
    00H
    Indeterminate
    0XXX0000B
    OTHER INFORMATION
    Reset
    The reset input is the RST pin, which is the input to a
    Schmitt Trigger.
    A reset is accomplished by holding the RST pin high for at
    least two machine cycles (24 oscillator periods), while the
    oscillator is running The CPU responds by generating an
    internal reset, with the timing shown in Figure 18.
    The external reset signal is asynchronous to the internal
    clock. The RST pin is sampled during State 5 Phase 2 of
    every machine cycle. The port pins will maintain their
    current activities for 19 oscillator periods after a logic 1 has
    been sampled at the RST pin; that is, for 19 to 31 oscillator
    periods after the external reset signal has been applied to
    the RST pin.
    The internal reset algorithm writes 0s to all the SFRs
    except the port latches, the Stack Pointer, and SBUF. The
    port latches are initialized to FFH, the Stack Pointer to 07H,
    and SBUF is indeterminate. Table 9 lists the SFRs and
    their reset values.
    Then internal RAM is not affected by reset. On power-up
    the RAM content is indeterminate.
    Figure 18. Reset Timing
    12 OSC. PERIODS
    ALE
    RST
    SAMPLE
    RST
    SAMPLE
    RST
    INTERNAL RESET SIGNAL
    PSEN
    P0
    11 OSC. PERIODS
    INST
    ADDR
    INST
    INST
    INST
    19 OSC. PERIODS
    S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4
    ADDR
    ADDR
    ADDR
    INST
    ADDR
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