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參數(shù)資料
| 型號(hào)： | IS80LV52-40WI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 11/48頁 |
| 文件大?。?/td> | 408K |
| 代理商： | IS80LV52-40WI |
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IS80LV52
IS80LV32
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION
MC019-0A
10/01/98
11
ISSI
The detail description of each bit is as follows:
PSW:
Program Status Word. Bit Addressable.
7
CY
6
5
4
3
2
1
—
0
P
AC
F0
RS1
RS0
OV
Register Description:
CY
PSW.7
AC
PSW.6
F0
PSW.5
Carry flag.
Auxiliary carry flag.
Flag 0 available to the user for
general purpose.
Register bank selector bit 1.
(1)
Register bank selector bit 0.
(1)
Overflow flag.
Usable as a general purpose flag
Parity flag. Set/Clear by hardware each
instruction cycle to indicate an odd/even
number of “1” bits in the accumulator.
RS1
RS0
OV
—
P
PSW.4
PSW.3
PSW.2
PSW.1
PSW.0
Note:
1. The value presented by RS0 and RS1 selects the corre-
sponding register bank.
RS1
0
0
1
1
RS0
0
1
0
1
Register Bank
0
1
2
3
Address
00H-07H
08H-0FH
10H-17H
18H-1FH
PCON:
Power Control Register. Not Bit Addressable.
7
SMOD —
6
5
—
4
—
3
2
1
0
GF1
GF0
PD
IDL
Register Description:
SMOD
Double baud rate bit. If Timer 1 is used to generate
baud rate and SMOD=1, the baud rate is doubled
when the serial port is used in modes 1, 2, or 3.
—
Not implemented, reserve for future use.
(1)
—
Not implemented, reserve for future use.
(1)
—
Not implemented, reserve for future use.
(1)
GF1
General purpose flag bit.
GF0
General purpose flag bit.
PD
Power-down bit. Setting this bit activates power-
down operation in the IS80LV52/32.
IDL
Idle mode bit. Setting this bit activates idle mode
operation in the IS80LV52/32. If 1s are written to
PD and IDL at the same time, PD takes
precedence.
Note:
1. User software should not write 1s to reserved bits. These bits
may be used in future products to invoke new features.
IE:
Interrupt Enable Register. Bit Addressable.
7
EA
6
—
5
4
3
2
1
0
ET2
ES
ET1
EX1
ET0 EX0
Register Description:
EA
IE.7
Disable all interrupts. If EA=0, no
interrupt will be acknowledged. If
EA=1, each interrupt source is
individually enabled or disabled by
setting or clearing its enable bit.
Not implemented, reserve for future
use.
(5)
Enables or disables timer 2 overflow
interrupt.
Enable or disable the serial port
interrupt.
Enable or disable the timer 1 overflow
interrupt.
Enable or disable external interrupt 1.
Enable or disable the timer 0 overflow
interrupt.
Enable or disable external interrupt 0.
—
IE.6
ET2
IE.5
ES
IE.4
ET1
IE.3
EX1
ET0
IE.2
IE.1
EX0
IE.0
Note:
To use any of the interrupts in the 80C51 Family, the following
three steps must be taken:
1. Set the
EA
(enable all) bit in the IE register to 1.
2. Set the coresponding individual interrupt enable bit in the IE
register to 1.
3. Begin the interrupt service routine at the corresponding
Vector Address of that interrupt (see below).
Interrupt Source
IE0
TF0
IE1
TF1
RI & TI
TF2 and EXF2
Vector Address
0003H
000BH
0013H
001BH
0023H
002BH
4. In addition, for external interrupts, pins INT0 and INT1 (P3.2
and P3.3) must be set to 1, and depending on whether the
interrupt is to be level or transition activated, bits IT0 or IT1
in the TCON register may need to be set to 0 or 1.
ITX = 0 level activated (X = 0, 1)
ITX = 1 transition activated
5. User software should not write 1s to reserved bits. These bits
may be used in future products to invoke new features.
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