FN2950.3 April 26, 2006 NOTES: 1. TBRE bit D6 in USR is updated each time TBRE changes state. 2. A. With TR initially empty, TCLTH(TBRE) occurs" />
參數(shù)資料
型號: IS82C52
廠商: Intersil
文件頁數(shù): 9/20頁
文件大?。?/td> 0K
描述: IC PERIPH UART/BRG 16MHZ 28-PLCC
標準包裝: 37
特點: 單芯片 UART/BRG
通道數(shù): 1,UART
規(guī)程: RS232C
電源電壓: 4.5 V ~ 5.5 V
帶并行端口:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應商設備封裝: 28-PLCC(11.51x11.51)
包裝: 管件
17
FN2950.3
April 26, 2006
NOTES:
1. TBRE bit D6 in USR is updated each time TBRE changes state.
2. A. With TR initially empty, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after WR goes high.
B. With TR initially full, TCLTH(TBRE) occurs from the trailing edge of the 15th CO(BRG) in the last Stop bit provided WR went high by the
trailing edge of the 12th CO(BRG) in the last Stop bit.
3. A. With TR (Transmitter Register) initially empty, TDTX occurs from the 5th falling edge of CO(BRG) after WR goes high.
B. With TR initially full, TDTX occurs from the trailing edge of the 16th CO(BRG) in the last Stop bit provided WR went high by the trailing edge
of the 12th CO(BRG) in the last Stop bit.
4. TCTHX is time before end of last Stop bit by which CTS must be inactive (high) to prevent transmission of the character waiting in TBR.
5. With CTS high (disable transmit) and TBR full, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after CTS goes low.
6. With CTS high (disable transmit) and TBR full, TDTX occurs from the 5th falling edge of CO(BRG) after CTS goes low.
FIGURE 19. RECEIVE TIMING
UART Timing Characterization (Continued)
CO(BRG)
SDI
DR
INTR
11
12
13
14
15
16
1/I
2/I
3/I
(23)
TRLIL
(26)
TRLDL
USR
RBR
START BIT / IDLE
(25)
TDRH
(21)
TIHF
RD
LAST STOP BIT
NOTE 1
NOTE 2
82C52
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