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參數(shù)資料
| 型號(hào)： | IS82C55AZ96 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 26/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER 24B 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接口： | 可編程 |
| 輸入/輸出數(shù)： | 24 |
| 中斷輸出： | 無(wú) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 1243 (CN2011-ZH PDF) |
| 其它名稱： | IS82C55AZ96DKR |
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6
FN2969.10
November 16, 2006
The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be “tailored” to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display
computational results, Group A could be programmed in
Mode 1 to monitor a keyboard or tape reader on an interrupt-
driven basis.
The mode definitions and possible mode combinations may
seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the 82C55A has taken into account
things such as efficient PC board layout, control signal
definition vs. PC layout and complete functional flexibility to
support almost any peripheral device with no external logic.
Such design represents the maximum use of the available
pins.
Single Bit Set/Reset Feature (Figure 5)
Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software
requirements in control-based applications.
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.
Interrupt Control Functions
When the 82C55A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from port C, can be inhibited or enabled
by setting or resetting the associated INTE flip-flop, using
the bit set/reset function of port C.
This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.
INTE Flip-Flop Definition
(BIT-SET)-INTE is SET - Interrupt Enable
(BIT-RESET)-INTE is Reset - Interrupt Disable
NOTE: All Mask flip-flops are automatically reset during mode
selection and device Reset.
Operating Modes
Mode 0 (Basic Input/Output). This functional configuration
provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply
written to or read from a specific port.
Mode 0 Basic Functional Definitions:
Two 8-bit ports and two 4-bit ports
Any Port can be input or output
Outputs are latched
Inputs are not latched
16 different Input/Output configurations possible
FIGURE 5. BIT SET/RESET FORMAT
D7 D6 D5
D4 D3 D2 D1 D0
BIT SET/RESET
1 = SET
0 = RESET
BIT SELECT
0
BIT SET/RESET FLAG
CONTROL WORD
DON’T
CARE
X
0 = ACTIVE
1 2345 67
01 0101 01
00 1100 11
00 0011 11
B0
B1
B2
MODE 0 PORT DEFINITION
A
B
GROUP A
#
GROUP B
D4
D3
D1
D0
PORT A
PORTC
(Upper)
PORT B
PORTC
(Lower)
0
Output
0
Output
0
1
Output
1
Output
Input
0
1
0
Output
2
Input
Output
0
1
Output
3
Input
0
1
0
Output
Input
4
Output
0
1
0
1
Output
Input
5
Output
Input
0
1
0
Output
Input
6
Input
Output
0
1
Output
Input
7
Input
1
0
Input
Output
8
Output
1
0
1
Input
Output
9
Output
Input
1
0
1
0
Input
Output
10
Input
Output
1
0
1
Input
Output
11
Input
1
0
Input
12
Output
1
0
1
Input
13
Output
Input
1
0
Input
14
Input
Output
1
Input
15
Input
82C55A
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