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參數(shù)資料
| 型號(hào)： | IS82C59A-12X96 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 21/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR INTERRPT 12.5MHZ 28PLCC |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 控制器類型： | CMOS 優(yōu)先中斷控制器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 1mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
8
FN2784.5
March 17, 2006
When interval = 4 bits, A5 - A7 are programmed, while
A0 - A4 are automatically inserted by the 82C59A. When
interval = 8, only A6 and A7 are programmed, while A0 - A5
are automatically inserted.
During the third INTA pulse, the higher address of the
appropriate service routine, which was programmed as byte 2
of the initialization sequence (A8 - A15), is enabled onto the
bus.
80C86, 8OC88, 80C286 Interrupt Response Mode
80C86/88/286 mode is similar to 8080/85 mode except that
only two Interrupt Acknowledge cycles are issued by the
processor and no CALL opcode is sent to the processor. The
first interrupt acknowledge cycle is similar to that of 8080/85
systems in that the 82C59A uses it to internally freeze the
state of the interrupts for priority resolution and, as a master,
it issues the interrupt code on the cascade lines. On this first
cycle, it does not issue any data to the processor and leaves
its data bus buffers disabled. On the second interrupt
acknowledge cycle in the 86/88/286 mode, the master (or
slave if so programmed) will send a byte of data to the
processor with the acknowledged interrupt code composed
as follows (note the state of the ADI mode control is ignored
and A5 - A11 are unused in the 86/88/286 mode).
Programming the 82C59A
The 82C59A accepts two types of command words
generated by the CPU:
1. Initialization Command Words (ICWs): Before normal
operation can begin, each 82C59A in the system must be
brought to a starting point - by a sequence of 2 to 4 bytes
timed by WR pulses.
2. Operation Command Words (OCWs): These are the
command words which command the 82C59A to operate
in various interrupt modes. Among these modes are:
a. Fully nested mode.
b. Rotating priority mode.
c. Special mask mode.
d. Polled mode.
The OCWs can be written into the 82C59A anytime after
initialization.
Initialization Command Words (lCWs)
General
Whenever a command is issued with A0 = 0 and D4 = 1, this
is interpreted as Initialization Command Word 1 (lCW1).
lCW1 starts the initialization sequence during which the
following automatically occur:
a. The edge sense circuit is reset, which means that follow-
ing initialization, an interrupt request (IR) input must make
a low-to-high transition to generate an interrupt.
b. The Interrupt Mask Register is cleared.
c. lR7 input is assigned priority 7.
d. Special Mask Mode is cleared and Status Read is set to
lRR.
CONTENT OF SECOND INTERRUPT VECTOR BYTE
IR
INTERVAL = 4
D7
D6
D5
D4
D3
D2
D1
D0
7
A7
A6
A5
11100
6
A7
A6
A5
11000
5
A7
A6
A5
10100
4
A7
A6
A5
10000
3
A7
A6
A5
01100
2
A7
A6
A5
01000
1
A7
A6
A5
00100
0
A7
A6
A5
00000
IR
INTERVAL = 8
D7
D6
DS
D4
D3
D2
D1
D0
7
A7
A6
111000
6
A7
A6
110000
5
A7
A6
101000
4
A7
A6
100000
3
A7
A6
011000
2
A7
A6
010000
1
A7
A6
001000
0
A7
A6
000000
CONTENT OF THIRD INTERRUPT VECTOR BYTE
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
A8
CONTENT OF INTERRUPT VECTOR BYTE FOR
80C86/88/286 SYSTEM MODE
D7
D6
D5
D4
D3
D2
D1
D0
lR7
T7T6T5T4T3
1
lR6
T7T6T5T4T3
1
0
IR5
T7T6T5T4T3
1
0
1
IR4
T7T6T5T4T3
1
0
IR3
T7T6T5T4T3
0
1
IR2
T7T6T5T4T3
0
1
0
IR1
T7T6T5T4T3
0
1
IR0
T7T6T5T4T3
0
82C59A
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