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參數(shù)資料
| 型號： | IS82C59A-12Z96 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 19/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR INTERRPT 12.5MHZ 28PLCC |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 控制器類型： | CMOS 優(yōu)先中斷控制器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 1mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
6
FN2784.5
March 17, 2006
Interrupt Request Register (IRR) and In-Service Register
(ISR)
The interrupts at the IR input lines are handled by two registers
in cascade, the Interrupt Request Register (lRR) and the In-
Service Register (lSR). The IRR is used to indicate all the
interrupt levels which are requesting service, and the ISR is
used to store all the interrupt levels which are currently being
serviced.
Priority Resolver
This logic block determines the priorities of the bits set in the
lRR. The highest priority is selected and strobed into the
corresponding bit of the lSR during the INTA sequence.
Interrupt Mask Register (IMR)
The lMR stores the bits which disable the interrupt lines to be
masked. The IMR operates on the output of the IRR.
Masking of a higher priority input will not affect the interrupt
request lines of lower priority.
Interrupt (INT)
This output goes directly to the CPU interrupt input. The
VOH level on this line is designed to be fully compatible with
the 8080, 8085, 8086/88, 80C86/88, 80286, and 80C286
input levels.
Interrupt Acknowledge (INTA)
INTA pulses will cause the 82C59A to release vectoring
information onto the data bus. The format of this data
depends on the system mode (
PM) of the 82C59A.
Data Bus Buffer
This 3-state, bidirectional 8-bit buffer is used to interface the
82C59A to the System Data Bus. Control words and status
information are transferred through the Data Bus Buffer.
Read/Write Control Logic
The function of this block is to accept output commands from
the CPU. It contains the Initialization Command Word (lCW)
registers and Operation Command Word (OCW) registers
which store the various control formats for device operation.
This function block also allows the status of the 82C59A to
be transferred onto the Data Bus.
Chip Select (CS)
A LOW on this input enables the 82C59A. No reading or
writing of the device will occur unless the device is selected.
Write (WR)
A LOW on this input enables the CPU to write control words
(lCWs and OCWs) to the 82C59A.
Read (RD)
A LOW on this input enables the 82C59A to send the status
of the Interrupt Request Register (lRR), In-Service Register
(lSR), the Interrupt Mask Register (lMR), or the interrupt
level (in the poll mode) onto the Data Bus.
A0
This input signal is used in conjunction with WR and RD
signals to write commands into the various command
registers, as well as to read the various status registers of
the chip. This line can be tied directly to one of the system
address lines.
The Cascade Buffer/Comparator
This function block stores and compares the IDs of all
82C59As used in the system. The associated three I/O pins
(CAS0 - 2) are outputs when the 82C59A is used as a
master and are inputs when the 82C59A is used as a slave.
As a master, the 82C59A sends the ID of the interrupting
slave device onto the CAS0 - 2 lines. The slave, thus
selected will send its preprogrammed subroutine address
onto the Data Bus during the next one or two consecutive
INTA pulses. (See section “Cascading the 82C59A”.)
Interrupt Sequence
The powerful features of the 82C59A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or indirect
jumping to the specified interrupt routine requested without
any polling of the interrupting devices. The normal sequence
of events during an interrupt depends on the type of CPU
being used.
82C59A
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