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參數資料
| 型號： | IS82C59AZX96 |
| 廠商： | Intersil |
| 文件頁數： | 17/22頁 |
| 文件大小： | 0K |
| 描述： | IC CTRLR INTERRUPT 8MHZ 28-PLCC |
| 標準包裝： | 750 |
| 控制器類型： | CMOS 優(yōu)先中斷控制器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 1mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
4
FN2784.5
March 17, 2006
Functional Description
Interrupts in Microcomputer Systems
Microcomputer system design requires that I/O devices such
as keyboards, displays, sensors and other components
receive servicing in an efficient manner so that large
amounts of the total system tasks can be assumed by the
microcomputer with little or no effect on throughput.
The most common method of servicing such devices is the
Polled approach. This is where the processor must test each
device in sequence and in effect “ask” each one if it needs
servicing. It is easy to see that a large portion of the main
program is looping through this continuous polling cycle and
that such a method would have a serious, detrimental effect
on system throughput, thus, limiting the tasks that could be
assumed by the microcomputer and reducing the cost
effectiveness of using such devices.
Pin Description
SYMBOL
TYPE
DESCRIPTION
VCC
I
VCC: The +5V power supply pin. A 0.1F capacitor between pins 28 and 14 is recommended for decoupling.
GND
I
GROUND
CS
I
CHIP SELECT: A low on this pin enables RD and WR communications between the CPU and the 82C59A. INTA
functions are independent of CS.
WR
I
WRITE: A low on this pin when CS is low enables the 82C59A to accept command words from the CPU.
RD
I
READ: A low on this pin when CS is low enables the 82C59A to release status onto the data bus for the CPU.
D7 - D0
I/O
BIDIRECTIONAL DATA BUS: Control, status, and interrupt-vector information is transferred via this bus.
CAS0 - CAS2
I/O
CASCADE LINES: The CAS lines form a private 82C59A bus to control a multiple 82C59A structure. These
pins are outputs for a master 82C59A and inputs for a slave 82C59A.
SP/EN
I/O
SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode it can be used
as an output to control buffer transceivers (EN). When not in the Buffered Mode it is used as an input to
designate a master (SP = 1) or slave (SP = 0).
INT
O
INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU,
thus, it is connected to the CPU's interrupt pin.
IR0 - IR7
I
INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an IR input (low to
high), and holding it high until it is acknowledged (Edge Triggered Mode), or just by a high level on an IR input
(Level Triggered Mode). Internal pull-up resistors are implemented on IR0 - 7.
INTA
I
INTERRUPT ACKNOWLEDGE: This pin is used to enable 82C59A interrupt-vector data onto the data bus by
a sequence of interrupt acknowledge pulses issued by the CPU.
A0
I
ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the 82C59A to
decipher various Command Words the CPU writes and status the CPU wishes to read. It is typically connected
to the CPU A0 address line (A1 for 80C86/88/286).
ROM
I/O (N)
I/O (2)
I/O (1)
RAM
CPU
CPU - DRIVEN
MULTIPLEXER
FIGURE 2. POLLED METHOD
82C59A
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