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| 型號(hào)： | IS9-1825ASRH-Q |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 穩(wěn)壓器 |
| 英文描述： | Single Event and Total Dose Hardened, High-Speed, Dual Output PWM |
| 中文描述： | 1 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, CDFP20 |
| 封裝： | CERAMIC, DFP-20 |
| 文件頁(yè)數(shù)： | 2/2頁(yè) |
| 文件大?。?/td> | 133K |
| 代理商： | IS9-1825ASRH-Q |
2
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9065.1
June 14, 2005
Die Characteristics
DIE DIMENSIONS:
4310
μ
m x 5840
μ
m (170 mils x 230 mils)
Thickness: 483
μ
m
±
25.4
μ
m (19 mils
±
1 mil)
INTERFACE MATERIALS
Glassivation
Type: Phosphorus Silicon Glass (PSG)
Thickness: 8.0kA +/- 1.0kA
Top Metallization
Type: AlSiCu
Thickness: 16.0kA +/- 2kA
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Transistor Count:
585
Metallization Mask Layout
IS-1825ASRH
VC
VC
IS-1825ASRH
VREF
INV
NON-INV
E/A OUT
CLK/LEB
RT
CT
RAMP
SS
ILIM/SD
OGND
GND
OUT A
PGND
PGND
OUT B
VCC
Notes:
1.
Both the OGND (oscillator ground) and the GND (control circuit ground) pads must be bonded to ground.
These pads are both bonded to the GND pin on the packaged devices.
All double-sized bond pads must be double bonded for current sharing purposes.
2.
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