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    參數(shù)資料
    型號: IS93C46A-3G
    廠商: INTEGRATED SILICON SOLUTION INC
    元件分類: DRAM
    英文描述: 1,024-BIT SERIAL ELECTRICALLY ERASABLE PROM
    中文描述: 64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8
    封裝: SOIC-8
    文件頁數(shù): 2/13頁
    文件大?。?/td> 84K
    代理商: IS93C46A-3G
    2
    Integrated Silicon Solution, Inc. — www.issi.com —
    1-800-379-4774
    Rev. E
    06/07/04
    IS93C46A
    ISSI
    PIN CONFIGURATIONS
    8-Pin JEDEC SOIC “G”
    8-Pin JEDEC SOIC “GR”
    PIN DESCRIPTIONS
    CS
    Chip Select
    SK
    Serial Data Clock
    D
    IN
    Serial Data Input
    D
    OUT
    Serial Data Output
    ORG
    Organization Select
    NC
    Not Connected
    Vcc
    Power
    GND
    Ground
    instruction begins with a start bit of the logical “1” or
    HIGH. Following this are the opcode (2 bits),
    address field (6 or 7 bits), and data, if appropriate. The
    clock signal may be held stable at any moment to
    suspend the device at its last state, allowing clock-
    speed flexibility. Upon completion of bus
    communication, CS would be pulled LOW. The device
    then would enter Standby mode if no internal
    programming is underway.
    Read (READ)
    The READ instruction is the only instruction that outputs
    serial data on the D
    OUT
    pin. After the read instruction and
    address have been decoded, data is transferred from the
    selected memory register into a serial shift register. (Please
    note that one logical “0” bit precedes the actual 8 or 16-bit
    output data string.) The output on D
    OUT
    changes during the
    low-to-high transitions of SK (see Figure 3).
    Low Voltage Read
    The IS93C46A has been designed to ensure that data
    read operations are reliable in low voltage environments.
    They provide accurate operation with Vcc as low as 2.5V.
    Auto Increment Read Operations
    In the interest of memory transfer operation applications,
    the IS93C46A has been designed to output a continuous
    stream of memory content in response to a single read
    operation instruction. To utilize this function, the system
    asserts a read instruction specifying a start location ad-
    dress. Once the 8 or16 bits of the addressed register have
    been clocked out, the data in consecutively higher address
    locations is output. The address will wrap around continu-
    ously with CS HIGH until the chip select (CS) control pin is
    brought
    LOW
    . This allows for single instruction data dumps
    to be executed with a minimum of firmware overhead.
    Applications
    The IS93C46A is very popular in many high-volume
    applications which require low-power, low-density
    storage. Applications using this device include
    industrial controls, networking, and numerous other
    consumer electronics.
    Endurance and Data Retention
    The IS93C46A is designed for applications requiring up to
    1M programming cycles (WRITE, WRALL, ERASE and
    ERAL). It provides 40 years of secure data retention without
    power after the execution of 1M programming cycles.
    Device Operations
    The IS93C46A is controlled by a set of instructions
    which are clocked-in serially on the Din pin. Before
    each low-to-high transition of the clock (SK), the CS pin
    must have already been raised to HIGH, and the Din
    value must be stable at either LOW or HIGH. Each
    1
    2
    3
    4
    8
    7
    6
    5
    CS
    SK
    D
    IN
    D
    OUT
    VCC
    NC
    ORG
    GND
    1
    2
    3
    4
    8
    7
    6
    5
    NC
    VCC
    CS
    SK
    ORG
    GND
    D
    OUT
    D
    IN
    1
    2
    3
    4
    8
    7
    6
    5
    CS
    SK
    D
    IN
    D
    OUT
    VCC
    NC
    ORG
    GND
    (Rotated)
    8-Pin DIP, 8-Pin TSSOP
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