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| 型號： | ISDMICROTAD-16M |
| 文件頁數(shù)： | 3/26頁 |
| 文件大?。?/td> | 1522K |
| 代理商： | ISDMICROTAD-16M |
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ISD MicroTAD-16M
1
ISD
DETAILED DESCRIPTION
SPEECH/SOUND QUALITY
The ISD MicroTAD-16M ChipCorder is offered at 4.0
KHz sampling frequency.
The speech samples are stored directly into on-chip
nonvolatile memory without the digitization and
compression associated with other solutions. Di-
rect analog storage provides a natural sounding
reproduction of voice, music, tones, and sound
effects not available with most solid-state solu-
tions.
FLASH STORAGE
One of the benefits of ISD’s ChipCorder technology
is the use of on-chip nonvolatile memory, which pro-
vides zero-power message storage. The message
is retained for up to 100 years (typically) without
power. In addition, the device can be re-record-
ed (typically) over 100,000 times.
MICROCONTROLLER INTERFACE
A four-wire (SCLK, MOSI, MISO, SS) SPI interface is
provided for ISD MicroTAD-16M control and ad-
dressing functions. The ISD MicroTAD-16M is con-
figured to operate as a peripheral slave device,
with a microcontroller-based SPI bus interface.
Read/Write access to all the internal registers oc-
curs through this SPI interface. An interrupt signal
(INT) and internal read-only Status Register are pro-
vided for handshake purposes.
PROGRAMMING
The ISD MicroTAD-16M is also ideal for playback-
only applications, where single or multiple mes-
sage Playback is controlled through the SPI port.
Once the desired message configuration is creat-
ed, duplicates can easily be generated via an ISD
programmer or a 3rd party programmer.
PIN DESCRIPTIONS
VOLTAGE INPUTS (V
CCA
, V
CCD
)
To minimize noise, the analog and digital circuits
in the ISD MicroTAD-16M device use separate power
busses. These + 3 V busses are brought out to sep-
arate pins and should be tied together as close to
the supply as possible. In addition, these supplies
should be decoupled as close to the package as
possible.
GROUND INPUTS (V
SSA
, V
SSD
)
The ISD MicroTAD-16M utilizes separate analog
and digital ground busses. The analog ground (V
S-
SA
) pins should be tied together as close to the
package as possible and connected through a
low-impedance path to power supply ground.
The digital ground (V
SSD
) pin should be connected
through a separate low-impedance path to pow-
er supply ground. These ground paths should be
large enough to ensure that the impedance be-
tween the V
SSA
pins and the V
SSD
pin is less than
3
. The backside of the die is connected to V
SS
through the substrate resistance. In a chip-on-
board design, the die attach area must be con-
nected to V
SS
or left floating.
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