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| 型號： | ISL12020MIRZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 10/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR TEMP SNSR 20-DFN |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 4,000 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，夏令時，閏年，SRAM |
| 存儲容量： | 128B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-DFN（5.5x4.0） |
| 包裝： | 帶卷 (TR) |
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ISL12020M
18
FN6667.5
December 13, 2011
BATTERY VOLTAGE TRIP VOLTAGE REGISTER
(PWR_VBAT)
This register controls the trip points for the two VBAT alarms, with
levels set to approximately 85% and 75% of the nominal battery
level.
RESEAL BIT (RESEALB)
This is the Reseal bit for actively disconnecting VBAT pin from the
internal circuitry. Setting this bit allows the device to disconnect the
battery and eliminate standby current drain while the device is
unused. Once VDD is powered up, this bit is reset and the VBAT pin is
then connected to the internal circuitry.
The application for this bit involves placing the chip on a board
with a battery and testing the board. Once the board is tested
and ready to ship, it is desirable to disconnect the battery to keep
it fresh until the board or unit is placed into final use. Setting
RESEALB = “1” initiates the battery disconnect, and after VDD
power is cycled down and up again, the RESEAL bit is cleared to
“0”.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP<2:0>)
Three bits select the first alarm (85% of Nominal VBAT) level for the
battery voltage monitor. There are total of 7 levels that could be
selected for the first alarm. Any of the of levels could be selected as
the first alarm with no reference as to nominal battery voltage level.
See Table 9.
BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)
Three bits select the second alarm (75% of Nominal VBAT) level for
the battery voltage monitor. There are total of 7 levels that could be
selected for the second alarm. Any of the of levels could be selected
as the second alarm with no reference as to nominal Battery voltage
level. See Table 10.
Initial AT and DT setting Register (ITRO)
These bits are used to trim the initial error (at room temperature)
of the crystal. Both Digital Trimming (DT) and Analog Trimming
(AT) methods are available. The digital trimming uses clock pulse
skipping and insertion for frequency adjustment. Analog
trimming uses load capacitance adjustment to pull the oscillator
frequency. A range of +62.5ppm to -61.5ppm is possible with
combined digital and analog trimming.
Initial values for the ITR0 register are preset internally and
recalled to RAM registers on power-up. These values can be
overwritten by the user although this is not suggested as the
resulting temperature compensation performance will be
compromised. Aging adjustment is normally a few ppm and can
be handled by writing to the IATR section.
AGING AND INITIAL TRIM DIGITAL TRIMMING BITS
(IDTR0<1:0>)
These bits allow ±30.5ppm initial trimming range for the crystal
frequency. This is meant to be a coarse adjustment if the range
needed is outside that of the IATR control. See Table 11. The
IDTR0 register should only be changed while the TSE (Temp
Sense Enable) bit is “0”.
The ISL12020M has a preset Initial Digital Trimming value
corresponding to the crystal in the module. This value is recalled
on initial power-up and should never be changed for best
temperature compensation performance, although the user may
change this preset value to adjust for aging or board mounting
changes if so desired.
AGING AND INITIAL ANALOG TRIMMING BITS
(IATR0<5:0>)
The Initial Analog Trimming Register allows +32ppm to -31ppm
adjustment in 1ppm/bit increments. This enables fine frequency
TABLE 8.
ADDR 7
6
5
4
3
2
1
0
0Ah
D RESEALB
VB85T
p2
VB85T
p1
VB85T
p0
VB75T
p2
VB75T
p1
VB75T
p0
TABLE 9. VB85T ALARM LEVEL
VB85Tp2
VB85Tp1
VB85Tp0
BATTERY ALARM TRIP
LEVEL
(V)
00
0
2.125
0
1
2.295
0
1
0
2.550
0
1
2.805
1
0
3.060
1
0
1
4.250
1
0
4.675
TABLE 10. BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)
VB75Tp2
VB75Tp1
VB75Tp0
BATTERY ALARM TRIP
LEVEL
(V)
000
1.875
0
1
2.025
0
1
0
2.250
011
2.475
1
0
2.700
1
0
1
3.750
110
4.125
TABLE 11. IDTR0 TRIMMING RANGE
IDTR01
IDTR00
TRIMMING RANGE
00
Default/Disabled
0
1
+30.5ppm
10
0ppm
1
-30.5ppm
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| ISL12020MIRZ-T7A | 功能描述:實時時鐘 LDAL TIME CLK & TEMP COMPENSATED CR RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12021 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock with On Chip Temp Compensation 【5ppm |
| ISL12021CVZ | 功能描述:IC RTC LP BATT BACK SRAM 14TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 實時時鐘 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:時鐘/日歷 特點:警報器，閏年，SRAM 存儲容量:- 時間格式:HH:MM:SS（12/24 小時） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN EP 包裝:管件 |
| ISL12021IVZ | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock with On Chip Temp Compensation 【5ppm |
| ISL12022 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock with On Chip ±5ppm Temp Compensation |
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