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參數(shù)資料
| 型號(hào)： | ISL12024IBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR EEPROM 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 980 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，唯一 ID |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
11
FN6370.3
August 18, 2008
Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match. See “Device Operation” on page 12
and “Application Section” on page 20 for more information.
Control Registers (Non-Volatile)
The Control Bits and Registers described under this section
are non-volatile.
BL Register
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will
prevent write operations to one of eight segments of the
array. The partitions are described in Table 3.
INT Register: Interrupt Control and
Frequency Output Register
IM, AL1E, AL0E - Interrupt Control and Status Bits
There are two Interrupt Control bits, Alarm 1 Interrupt Enable
(AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically
enable or disable the alarm interrupt signal output
(IRQ/FOUT). The interrupts are enabled when either the
AL1E or AL0E or both bits are set to ‘1’ and both the FO1
and FO0 bits are set to 0 (FOUT disabled).
The IM bit enables the pulsed interrupt mode. To enter this
mode, the AL0E or AL1E bits are set to “1”, and the IM bit to
“1”. The IRQ/FOUT output will now be pulsed each time an
alarm occurs. This means that once the interrupt mode
alarm is set, it will continue to alarm for each occurring
match of the alarm and present time. This mode is
convenient for hourly or daily hardware interrupts in
microcontroller applications such as security cameras or
utility meter reading.
In this case both Alarms are enabled.
FO1, FO0 - Programmable Frequency Output Bits
These are two output control bits. They select one of three
divisions of the internal oscillator, that is applied to the
this output. When using this function, the Alarm output
function is disabled.
Oscillator Compensation Registers
There are two trimming options.
ATR. Analog Trimming Register
DTR. Digital Trimming Register
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64ppm to +110 ppm of
total adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34ppm
to +80ppm to the nominal frequency compensation.
TABLE 3.
BP2
BP1
BP0
PROTECTED ADDRESSES
ISL12024
ARRAY LOCK
0
None (Default)
None
0
1
180h – 1FFh
Upper 1/4
0
1
0
100h – 1FFh
Upper 1/2
0
1
000h – 1FFh
Full Array
1
0
000h – 03Fh
First 4 Pages
1
0
1
000h – 07Fh
First 8 Pages
1
0
000h – 0FFh
First 16 Pages
1
000h – 1FFh
Full Array
TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS
FO1
FO0
OUTPUT FREQUENCY
0
Alarm output (FOUT disabled)
0
1
32.768kHz
1
0
4096Hz
11
1Hz
FIGURE 8. DIAGRAM OF ATR
CX1
X1
X2
CRYSTAL
OSCILLATOR
CX2
ISL12024
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| ISL12024IBZ-T | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK/CLNDR W/EEPROM IN 8LD RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12024IRTCZ | 功能描述:實(shí)時(shí)時(shí)鐘 RTC OUTPUT PROGRAM TO 32KHZ W/EEPROM 8 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12024IRTCZ-T | 功能描述:實(shí)時(shí)時(shí)鐘 RTC OUTPUT PROGRAM TO 32KHZ W/EEPROM 8 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12024IVZ | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK/CLNDR W/EEPROM IN 8LD RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12024IVZ-T | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK/CLNDR W/EEPROM IN 8LD RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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