參數資料
| 型號： | ISL12025IBZ-T |
| 廠商： | Intersil |
| 文件頁數： | 7/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR EEPROM 8-SOIC |
| 標準包裝： | 2,500 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，監(jiān)控器，唯一 ID，監(jiān)視計時器 |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數據格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
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15
FN6371.3
August 13, 2008
Standard Mode Power Switchover
Normal Operating Mode (VDD) to Battery Backup Mode
(VBAT)
To transition from the VDD to VBAT mode, both of the
following conditions must be met:
- Condition 1:
VDD < VBAT - VBATHYS
where VBATHYS ≈ 50mV
- Condition 2:
VDD < VTRIP
where VTRIP ≈ 2.2V
Battery Backup Mode (VBAT) to Normal Mode (VDD)
The ISL12025 device will switch from the VBAT to VDD
mode when one of the following conditions occurs:
- Condition 1:
VDD > VBAT + VBATHYS
where VBATHYS ≈ 50mV
- Condition 2:
VDD > VTRIP + VTRIPHYS
where VTRIPHYS ≈ 30mV
There are two discrete situations that are possible when
using Standard Mode: VBAT < VTRIP and VBAT > VTRIP.
These two power control situations are illustrated in
OPTION 2 - LEGACY (POWER CONTROL) MODE
(DEFAULT)
The Legacy Mode follows conditions set in X1226 products.
In this mode, switching from VDD to VBAT is simply done by
comparing the voltages and the device operates from
whichever is the higher voltage. Care should be taken when
changing from Normal to Legacy Mode. If the VBAT voltage is
higher than VDD, then the device will enter battery back up
and unless the battery is disconnected or the voltage
decreases, the device will no longer operate from VDD.
To select the Option 2, BSW bit in the Power Register must
be set to “BSW = 1”.
Normal Mode (VDD) to Battery Backup Mode (VBAT)
To transition from the VDD to VBAT mode, the following
conditions must be met:
VDD < VBAT - VBATHYS
Battery Backup Mode (VBAT) to Normal Mode (VDD)
The device will switch from the VBAT to VDD mode when
the following condition occurs:
VDD > VBAT +VBATHYS
The Legacy Mode power control conditions are illustrated in
Figure 15.
Power-On Reset
Application of power to the ISL12025 activates a
Power-On-Reset Circuit that pulls the RESET pin active.
This signal provides several benefits.
- It prevents the system microprocessor from starting to
operate with insufficient voltage.
- It prevents the processor from operating prior to
stabilization of the oscillator.
- It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
- It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When VDD exceeds the device VRESET threshold value for
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
Watchdog Timer Operation
The Watchdog timer timeout period is selectable. By writing
a value to WD1 and WD0, the Watchdog timer can be set to
3 different time out periods or off. When the Watchdog timer
is set to off, the watchdog circuit is configured for low power
operation (see Table 6).
BATTERY BACKUP
MODE
VDD
2.2V
FIGURE 13. BATTERY SWITCHOVER WHEN VBAT < VTRIP
VBAT
VTRIP
1.8V
VBAT + VBATHYS
VBAT - VBATHYS
FIGURE 14. BATTERY SWITCHOVER WHEN VBAT > VTRIP
VTRIP
VBAT
VTRIP + VTRIPHYS
BATTERY BACKUP
MODE
VDD
VTRIP
3.0V
2.2V
VBAT
IN
VOLTAGE
VDD
ON
OFF
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
ISL12025
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