參數(shù)資料
型號(hào)： ISL12027IVZ-T
廠商： Intersil
文件頁(yè)數(shù)： 24/28頁(yè)
文件大小： 0K
描述： IC RTC/CALENDAR EEPROM 8-TSSOP
產(chǎn)品培訓(xùn)模塊： Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，閏年，監(jiān)控器，監(jiān)視計(jì)時(shí)器
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 8-TSSOP
包裝： 帶卷 (TR)
5
FN8232.8
August 12, 2010
Watchdog Timer/Low Voltage Reset Parameters
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 16)
TYP
(Note 5)
MA
(Note 16)
UNITS
NOTES
tRPD
VDD Detect to RESET LOW
500
ns
13
tPURST
Power-up Reset Time-Out Delay
100
250
400
ms
VRVALID Minimum VDD for Valid RESET
Output
1.0
V
VRESET
ISL12027-4.5A Reset Voltage Level
4.59
4.64
4.69
V
ISL12027 Reset Voltage Level
4.33
4.38
4.43
V
ISL12027-3 Reset Voltage Level
3.04
3.09
3.14
V
ISL12027-2.7A Reset Voltage Level
2.87
2.92
2.97
V
ISL12027-2.7 Reset Voltage Level
2.58
2.63
2.68
V
tWDO
Watchdog Timer Period
32.768kHz crystal between X1
and X2
1.70
1.75
1.801
s
725
750
775
ms
225
250
275
ms
tRST
Watchdog Timer Reset Time-Out
Delay
32.768kHz crystal between X1
and X2
225
250
275
ms
tRSP
I2C Interface Minimum Restart Time
1.2
s
EEPROM SPECIFICATIONS
EEPROM Endurance
>2,000,000
Cycles
EEPROM Retention
Temperature
≤ +75°C
50
Years
Serial Interface (I2C) Specifications
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
VIL
SDA, and SCL Input Buffer LOW
Voltage
SBIB = 1 (Under VDD mode)
-0.3
0.3xVDD
V
VIH
SDA, and SCL Input Buffer HIGH
Voltage
SBIB = 1 (Under VDD mode)
0.7xVDD
VDD + 0.3
V
Hysteresis SDA and SCL Input Buffer
Hysteresis
SBIB = 1 (Under VDD mode)
0.05xVDD
V
VOL
SDA Output Buffer LOW Voltage
IOL = 4mA
0
0.4
V
ILI
Input Leakage Current on SCL
VIN = 5.5V
0.1
10
A
ILO
I/O Leakage Current on SDA
VIN = 5.5V
0.1
10
A
TIMING CHARACTERISTICS
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec
is suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of VDD,
until SDA exits the 30% to 70% of VDD
window.
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing 70%
of VDD during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD crossing.
600
ns
ISL12027, ISL12027A
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