The effective on-chip series load capacitance, CLOAD,
參數(shù)資料
型號(hào): ISL12029IV30AZ
廠商: Intersil
文件頁(yè)數(shù): 6/29頁(yè)
文件大?。?/td> 0K
描述: IC RTC/CALENDAR EEPROM 14-TSSOP
標(biāo)準(zhǔn)包裝: 960
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,監(jiān)控器,監(jiān)視計(jì)時(shí)器
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 管件
14
FN6206.10
December 16, 2010
The effective on-chip series load capacitance, CLOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). CLOAD is changed via two digitally
controlled capacitors, CX1 and CX2, connected from the X1
and X2 pins to ground (see Figure 11). The value of CX1 and
CX2 is given by Equation 1:
The effective series load capacitance is the combination of
CX1 and CX2 given in Equation 2:
For example, CLOAD(ATR = 00000) = 12.5pF,
CLOAD(ATR = 100000) = 4.5pF, and CLOAD(ATR = 011111) =
20.25pF. The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note
that these are typical values.
DTR Register - DTR2, DTR1, DTR0: Digital
Trimming Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit. DTR2 = 0 means frequency
compensation is > 0. DTR2 = 1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10ppm
adjustment and DTR0 gives 20ppm adjustment.
A range from -30ppm to +30ppm can be represented by
using the three DTR bits.
PWR Register: SBIB, BSW, VTS2, VTS1, VTS0
SBIB: Serial Bus Interface (Enable)
The serial bus can be disabled in battery backup mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in battery
backup mode by setting this bit to “0”. (default is “0”). See
BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for
switching between VDD and Back Up Battery. There are two
options.
Option 1 Standard Mode: Set “BSW = 0” (default for
ISL12029A)
Option 2 Legacy/Default Mode: Set “BSW = 1” (default for
ISL12029)
LVR Operation” on page 25 for important details.
VTS2, VTS1, VTS0: VRESET Select Bits
The ISL12029 is shipped with a default VDD threshold
(VRESET) per the ordering information table. This register is
a non-volatile with no protection, therefore any writes to this
location can change the default value from that marked on
the package. If not changed with a non-volatile write, this
value will not change over normal operating and storage
conditions. However, ISL12029 has four (4) additional
selectable levels to fit the customers application. Levels are:
4.64V(default), 4.38V, 3.09V, 2.92V and 2.63V. The VRESET
selection is via 3 bits (VTS2, VTS1 and VTS0) (see Table 6).
Care should be taken when changing the VRESET select bits.
If the VRESET voltage selected is higher than VDD, then the
device will go into RESET and unless VDD is increased, the
device will no longer be able to communicate using the I2C
bus.
TABLE 5. DIGITAL TRIMMING REGISTERS
DTR REGISTER
ESTIMATED FREQUENCY
PPM
DTR2
DTR1
DTR0
00
0
FIGURE 12. DIAGRAM OF ATR
CX1
X1
X2
CRYSTAL
OSCILLATOR
CX2
C
X
16 b5
8b4
4 b3
2b2
1 b1
0.5b0
9
+
+
+
+
+
+
()pF
=
(EQ. 1)
C
LOAD
1
C
X1
-----------
1
C
X2
-----------
+
-----------------------------------
=
C
LOAD
16 b5
8 b4
4 b3
2 b2
1 b1
0.5 b0
9
+
+
+
+
+
+
2
-----------------------------------------------------------------------------------------------------------------------------
pF
=
(EQ. 2)
01
0
+10
00
1
+20
01
1
+30
10
0
11
0
-10
10
1
-20
11
1
-30
TABLE 5. DIGITAL TRIMMING REGISTERS (Continued)
DTR REGISTER
ESTIMATED FREQUENCY
PPM
DTR2
DTR1
DTR0
ISL12029, ISL12029A
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