參數(shù)資料
型號(hào)： ISL12029IVAZ
廠商： Intersil
文件頁(yè)數(shù)： 10/29頁(yè)
文件大小： 0K
描述： IC RTC/CALENDAR EEPROM 14-TSSOP
標(biāo)準(zhǔn)包裝： 960
類型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，閏年，監(jiān)控器，監(jiān)視計(jì)時(shí)器
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 管件
18
FN6206.10
December 16, 2010
In battery mode, the RESET signal output is asserted LOW
when the VDD voltage supply has dipped below the VRESET
threshold. The RESET signal output will not return HIGH
until the device is back to VDD mode even the VDD voltage is
above VRESET threshold.
Serial Communication
The device supports the I2C bidirectional serial bus protocol.
CLOCK AND DATA
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (see Figure 16).
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met (see Figure 17).
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus (see Figure 17).
ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8-bits.
During the ninth clock cycle, the receiver will pull the SDA
line LOW to acknowledge that it received the 8-bits of data
(refer to Figure 18).
The device will respond with an acknowledge after recognition
of a start condition and if the correct Device Identifier and Select
bits are contained in the Slave Address Byte. If a write
operation is selected, the device will respond with an
acknowledge after the receipt of each subsequent 8-bit word.
The device will not acknowledge if the slave address byte is
incorrect.
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
SCL
SDA
START
STOP
FIGURE 17. VALID START AND STOP CONDITIONS
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
8
1
9
START
ACKNOWLEDGE
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
ISL12029, ISL12029A
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