tIN Pulse width Suppression Time at SDA and SCL Inputs Any pulse narrower than" />
參數(shù)資料
型號： ISL12058IRUZ-T
廠商： Intersil
文件頁數(shù)： 15/19頁
文件大小： 0K
描述： IC RTC/CALENDAR I2C-BUS 8-UTDFN
標準包裝： 3,000
類型： 時鐘/日歷
特點： 警報器，閏年
時間格式： HH:MM:SS（12/24 小時）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 1.8 V ~ 3.6 V
電壓 - 電源，電池： 1.4 V ~ 1.8 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-UFDFN
供應(yīng)商設(shè)備封裝： 8-µTDFN（2x2）
包裝： 帶卷 (TR)
5
FN6756.0
June 15, 2009
tIN
Pulse width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max
spec is suppressed
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of
VDD, until SDA exits the 30% to
70% of VDD window
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing
70% of VDD during the following
START condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling
edge. Both crossing 70% of VDD
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70%
of VDD window, to SCL rising edge
crossing 30% of VDD
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing
30% of VDD to SDA entering the
30% to 70% of VDD window
0
900
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing
70% of VDD, to SDA rising edge
crossing 30% of VDD
600
ns
tHD:STO
STOP Condition Hold Time
From SDA rising edge to SCL
falling edge. Both crossing 70% of
VDD
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing
30% of VDD, until SDA enters the
30% to 70% of VDD window
0ns
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 + 0.1 x Cb
300
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 + 0.1 x Cb
300
ns
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
Rpu
SDA and SCL Bus Pull-Up
Resistor Off-Chip
Maximum is determined by tR and
tF.
For Cb = 400pF, max is about
2k
Ω to~2.5kΩ.
For Cb = 40pF, max is about 15k
Ω
to ~20k
Ω
1k
Ω
NOTES:
6. IRQ/FOUT inactive.
7. Typical values are for T = +25°C and 3.3V supply voltage.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
9. Limits should be considered typical and are not production tested.
10. These are I2C specific parameters and are not production tested, however, they are used to set conditions for testing devices to
validate specification.
11. Parts will work with SDA pull-up voltage above the VPULLUP limit but the tAA and tFin the I
2C parameters are not guaranteed.
12. Specified at +25°C.
Serial Interface Specifications
Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP (Note 7)
MAX
(Note 8)
UNITS
NOTES
ISL12058
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