參數(shù)資料
型號: ISL1208IU8Z
廠商: Intersil
文件頁數(shù): 8/24頁
文件大?。?/td> 0K
描述: IC RTC LP BATT BACKED SRAM 8MSOP
標(biāo)準(zhǔn)包裝: 80
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,SRAM
存儲容量: 2B
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 管件
產(chǎn)品目錄頁面: 1245 (CN2011-ZH PDF)
16
FN8085.8
September 12, 2008
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 13).
The ISL1208 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL1208 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
FIGURE 14. BYTE WRITE SEQUENCE
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE ISL1208
A
C
K
10
0
11
A
C
K
WRITE
SIGNAL AT SDA
00 00
11 1
ADDRESS
BYTE
ISL1208
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