2 FN7902.0 August 19, 2011 Block Diagram POWER UP INTERFACE, CONTROL AND STATUS LOGIC I/O BLOCK V
參數(shù)資料
型號(hào): ISL23328UFRUZ-T7A
廠商: Intersil
文件頁(yè)數(shù): 12/20頁(yè)
文件大?。?/td> 0K
描述: IC DGTL POT 2CH 50K 16UTQFN
標(biāo)準(zhǔn)包裝: 1
系列: XDCP™
接片: 128
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 65 ppm/°C
存儲(chǔ)器類(lèi)型: 易失
接口: I²C(設(shè)備位址)
電源電壓: 1.2 V ~ 5.5 V,1.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-UFQFN
供應(yīng)商設(shè)備封裝: 16-UTQFN(2.6x1.8)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱(chēng): ISL23328UFRUZ-T7ADKR
ISL23328
2
FN7902.0
August 19, 2011
Block Diagram
POWER UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
I/O
BLOCK
VCC
GND
SCL
SDA
A0
A1
RH0
RL0
RW0
RH1
RL1
RW1
WR0
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
WR1
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
A2
VLOGIC
LEVEL
SHIFTER
Pin Configurations
ISL23328
(14 LD TSSOP)
TOP VIEW
ISL23328
(16 LD UTQFN)
TOP VIEW
SDA
VLOGIC
A0
VCC
SCL
GND
RL1
RW1
RH1
A1
RL0
A2
RH0
RW0
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A2
V
LOG
IC
RH1
GND
NC
RL
1
RW1
V
CC
A1
RW0
SCL
RH0
RL
0
SDA
A0
1
3
4
15
16
14
13
2
12
10
9
11
6
5
7
8
GND
Pin Descriptions
TSSOP
UTQFN
SYMBOL
DESCRIPTION
1
6, 15
GND
Ground pin
216
VLOGIC
I2C bus/logic supply. Range 1.2V to
5.5V
3
1
SDA
Logic Pin - Serial bus data
input/open drain output
4
2
SCL
Logic Pin - Serial bus clock input
5
3
A0
Logic Pin - Hardwire slave address
pin for I2C serial bus.
Range: VLOGIC or GND
6
4
A1
Logic Pin - Hardwire slave address
pin for I2C serial bus.
Range: VLOGIC or GND
7
5
A2
Logic Pin - Hardwire slave address
pin for I2C serial bus.
Range: VLOGIC or GND
8
RL1
DCP1 “l(fā)ow” terminal
9
RW1
DCP1 wiper terminal
10
RH1
DCP1 “high” terminal
11
RH0
DCP0 “high” terminal
12
RW0
DCP0 wiper terminal
13
RL0
DCP0 “l(fā)ow” terminal
14
VCC
Analog power supply.
Range 1.7V to 5.5V
7NC
Not Connected
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