13 FN7903.1 August 24, 2011 Functional Pin Descriptions Potentiometers Pins RHI
參數(shù)資料
型號: ISL23348TFVZ-TK
廠商: Intersil
文件頁數(shù): 5/19頁
文件大小: 0K
描述: IC DGTL POT 4CH 100K 20TSSOP
標準包裝: 1,000
系列: XDCP™
接片: 128
電阻(歐姆): 100k
電路數(shù): 4
溫度系數(shù): 標準值 45 ppm/°C
存儲器類型: 易失
接口: I²C(設備位址)
電源電壓: 1.2 V ~ 5.5 V,1.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 帶卷 (TR)
ISL23348
13
FN7903.1
August 24, 2011
Functional Pin Descriptions
Potentiometers Pins
RHI AND RLI
The high (RHi, i = 0, 1, 2, 3) and low (RLi, i = 0, 1, 2, 3) terminals
of the ISL23348 are equivalent to the fixed terminals of a
mechanical potentiometer. RHi and RLi are referenced to the
relative position of the wiper and not the voltage potential on the
terminals. With WRi set to 127 decimal, the wiper will be closest
to RHi, and with the WRi set to 0, the wiper is closest to RLi.
RWI
RWi (i = 0, 1, 3) is the wiper terminal, and it is equivalent to the
movable terminal of a mechanical potentiometer. The position of
the wiper within the array is determined by the WRi register.
VCC
Power terminal for the potentiometer section analog power source.
Can be any value needed to support the voltage range of the DCP
pins, from 1.7V to 5.5V, independent of the VLOGIC voltage.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for I2C
interface. It receives device address, wiper address and data
from an I2C external master device at the rising edge of the serial
clock SCL, and it shifts out data after each falling edge of the
serial clock.
SDA requires an external pull-up resistor, since it is an open drain
input/output.
SERIAL CLOCK (SCL)
This input is the serial clock of the I2C serial interface. SCL
requires an external pull-up resistor, since a master is an open
drain output.
DEVICE ADDRESS (A2, A1, A0)
The address inputs are used to set the least significant 3 bits of
the 7-bit I2C interface slave address. A match in the slave
address serial data stream must match with the Address input
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME
FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
FIGURE 23. 10k -3dB CUT OFF FREQUENCY
FIGURE 24. STANDBY CURRENT vs TEMPERATURE
Typical Performance Curves (Continued)
SCL 9TH CLOCK OF THE
DATA BYTE (ACK)
1V/DIV
0.2s/DIV
WIPER
SCL
0.5V/DIV
20s/DIV
VCC
WIPER
0.5V/DIV, 0.2s/DIV
-3dB FREQUENCY = 1.437MHz AT MIDDLE TAP
CH1: RH TERMINAL
CH2: RW TERMINAL
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-40
-15
10
35
60
85
110
VCC = 1.7V, VLOGIC = 1.2V
VCC = 5.5V, VLOGIC = 5.5V
S
TA
N
D
B
Y
C
U
R
E
N
T
IC
C
(
A
)
TEMPERATURE (°C)
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