7 FN7903.1 August 24, 2011 tDCP Wiper Response Time W option; SCL rising edge at the ac" />
參數(shù)資料
型號： ISL23348WFRZ-TK
廠商： Intersil
文件頁數(shù)： 17/19頁
文件大?。?/td> 0K
描述： IC DGTL POT 4CH 10K 20QFN
標(biāo)準(zhǔn)包裝： 1,000
系列： XDCP™
接片： 128
電阻（歐姆）： 10k
電路數(shù)： 4
溫度系數(shù)： 標(biāo)準(zhǔn)值 125 ppm/°C
存儲器類型： 易失
接口： I²C（設(shè)備位址）
電源電壓： 1.2 V ~ 5.5 V，1.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 20-QFN（3x4）
包裝： 帶卷 (TR)
ISL23348
7
FN7903.1
August 24, 2011
tDCP
Wiper Response Time
W option; SCL rising edge at the acknowledge bit
after data byte to wiper new position from 10% to
90% of the final value.
0.4
s
U option; SCL rising edge of the acknowledge bit
after data byte to wiper new position from 10% to
90% of the final value.
1.5
s
T option; SCL rising edge of the acknowledge bit
after data byte to wiper new position from 10% to
90% of the final value.
3.5
s
tShdnRec DCP Recall Time from Shutdown Mode
SCL rising edge of the acknowledge bit after ACR
data byte to wiper recalled position and RH
connection
1.5
s
VCC,VLOGIC
Ramp
(Note 21)
VCC ,VLOGIC Ramp Rate
Ramp monotonic at any level
0.01
50
V/ms
Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20) UNITS
Serial Interface Specification For SCL, SDA, A0, A1, A2 unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
UNITS
VIL
Input LOW Voltage
-0.3
0.3 x VLOGIC
V
VIH
Input HIGH Voltage
0.7 x VLOGIC
VLOGIC + 0.3
V
Hysteresis
SDA and SCL Input Buffer
Hysteresis
VLOGIC > 2V
0.05 x VLOGIC
V
VLOGIC < 2V
0.1 x VLOGIC
V
VOL
SDA Output Buffer LOW Voltage
IOL = 3mA, VLOGIC > 2V
0
0.4
V
IOL = 1.5mA, VLOGIC < 2V
0.2 x VLOGIC
V
Cpin
SDA, SCL Pin Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
tsp
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of VLOGIC, until
SDA exits the 30% to 70% of VLOGIC window
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VLOGIC during a STOP
condition, to SDA crossing 70% of VLOGIC during
the following START condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VLOGIC crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VLOGIC crossing
600
ns
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA falling edge; both crossing
70% of VLOGIC
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VLOGIC to
SCL falling edge crossing 70% of VLOGIC
600
ns
tSU:DAT
Input Data Set-up Time
From SDA exiting the 30% to 70% of VLOGIC
window, to SCL rising edge crossing 30% of
VLOGIC
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing 70% of VLOGIC to
SDA entering the 30% to 70% of VLOGIC window
0ns
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