2 FN7874.0 June 21, 2011 Block Diagram POWER UP INTERFACE CONTROL AND STATUS LOGIC I/O BLOCK V" />
參數(shù)資料
型號(hào): ISL23445UFVZ-T7A
廠商: Intersil
文件頁(yè)數(shù): 12/20頁(yè)
文件大小: 0K
描述: IC DGTL POT QUAD 50K 20TSSOP
產(chǎn)品培訓(xùn)模塊: Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝: 1
系列: XDCP™
接片: 256
電阻(歐姆): 50k
電路數(shù): 4
溫度系數(shù): 標(biāo)準(zhǔn)值 65 ppm/°C
存儲(chǔ)器類型: 易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 1.2 V ~ 5.5 V,1.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ISL23445UFVZ-T7ADKR
ISL23445
2
FN7874.0
June 21, 2011
Block Diagram
POWER UP
INTERFACE
CONTROL
AND
STATUS
LOGIC
I/O
BLOCK
VCC
GND
SDI
SDO
SCK
VLOGIC
LEVEL
SHIFTER
WR0
VOLATILE
REGISTER
WR1
VOLATILE
REGISTER
WR2
VOLATILE
REGISTER
WR3
VOLATILE
REGISTER
RH0
RW0
RL0
RH1
RW1
RL1
RH2
RW2
RL2
RH3
RW3
RL3
CS
Pin Configurations
ISL23445
(20 LD TSSOP)
TOP VIEW
ISL23445
(20 LD QFN)
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
RL0
RW0
VCC
RH0
RL1
RW1
GND
RH1
VLOGIC
SDI
RL3
RH3
RL2
RW2
RW3
RH2
SCK
SDO
GND
CS
V
LO
GIC
RW1
SCK
RH2
SDI
CS
RL0
RW
0
RL3
GND
RL2
RH0
RW2
RW
3
VCC
RL1
RH1
SDO
1
2
3
4
5
78
9
10
15
14
13
12
11
20
19
18
17
6
GND
6
RH3
16
Pin Descriptions
TSSOP
QFN
SYMBOL
DESCRIPTION
1
19
RL0
DCP0 “l(fā)ow” terminal
2
20
RW0
DCP0 wiper terminal
31
VCC
Analog power supply.
Range 1.7V to 5.5V
42
RH0
DCP0 “high” terminal
5
3
RL1
DCP1 “l(fā)ow” terminal
6
4
RW1
DCP1 wiper terminal
75
RH1
DCP1 “high” terminal
8, 12
6, 10
GND
Ground pin
97
VLOGIC
SPI bus /logic supply
Range 1.2V to 5.5V
10
8
SDI
Logic Pin - Serial bus data input
11
9
CS
Logic Pin - Active low chip select
13
11
SDO
Logic Pin - Serial bus data output
(configurable)
14
12
SCK
Logic Pin - Serial bus clock input
15
13
RH2
DCP2 “high” terminal
16
14
RW2
DCP2 wiper terminal
17
15
RL2
DCP2 “l(fā)ow” terminal
18
16
RH3
DCP3 “high” terminal
19
17
RW3
DCP3 wiper terminal
20
18
RL3
DCP3 “l(fā)ow” terminal
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