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參數(shù)資料
| 型號： | ISL24011IVZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 其它接口 |
| 英文描述： | High Voltage TFT-LCD Logic Driver |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PDSO20 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-20 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 284K |
| 代理商： | ISL24011IVZ |
7
FN6196.0
October 21, 2005
Application Information
General
The ISL24011 is an octal voltage level shifter. The part was
designed to level shift a digital input signal to +22V and -5V
for TFT-LCD displays and is capable of level shifting input
logic signals (0V to 5.5V) to outputs as large as +40V and
-20V.
Power Supply Decoupling
The ISL24011 requires a 1.0μF decoupling capacitor as
close to the V
ON1
, V
ON2
and V
OFF
power supply pins, as
possible, for a large load equal to 5k
in parallel with
4700pF (Figure 16). This will reduce any dv/dt between the
different supplies and prevent the internal ESD clamp from
turning on and damaging the part.
For lighter loads such as a series 200
resistor and a
3300pF capacitance, the decoupling capacitors can be
reduced to 0.47μF.
Power Supply Sequence
The ISL24011 requires that V
ON2
be greater than or equal to
V
ON1
at all times. Therefore, if V
ON1
and V
ON2
are different
supplies, then V
ON2
needs to be turned on before V
ON1
.
The reason for this requirement is shown in Circuit 4 in the
Pin Description Table. The ESD protection diode between
V
ON2
and V
ON1
will forward bias if V
ON1
becomes a diode
drop greater than V
ON2
. Recommended power supply
sequence: V
ON2
, V
ON1
, V
OFF
, then input logic signals.
The ESD protection scheme is based on diodes from the
pins to the V
ON2
supply and a dv/dt-triggered clamp. This
dv/dt-triggered clamp imposes a maximum supply turn-on
slew rate of 10V/μs. This clamp will trigger if the supply
powers up too fast, causing amps of current to flow. Ground
and V
ON1
are treated as I/O pins with this protection
scheme. In applications where the dv/dt supply ramp could
exceed 10V/μs, such as hot plugging, additional methods
should be employed to ensure the rate of rise is not
exceeded.
Latch-up Proof
The ISL24011 is manufactured in a high voltage DI process
that isolates every transistor in its own tub making the part
latch-up proof.
Input Pin Connections
Unused inputs must be tied to ground. Failure to tie unused
input pins to ground will result in rail to rail oscillations on the
respective output pins and higher unwanted power
dissipation in the part. Under these conditions, the
temperature of the part could get very hot.
Limiting the Output Current
No output short circuit current limit exists on this part. All
applications need to limit the output current to less than
80mA. Adequate thermal heat sinking of the parts is also
required.
Application Diagram (TV)
FIGURE 13. TRANSIENT RESPONSE vs LOAD CAPACITANCE
Typical Performance Curves
T
A
= 25°C, Output load parallel RC (RL = 5k
, CL = 4700pF) unless otherwise specified.
(Continued)
0
0
400ns/DIV
1800pF
4700pF
PULSE INPUT
2
5
50kHz 10% DUTY CYCLE
V
ON1
&
V
ON2
= 22V
V
OFF
= -5V
ISL24011
LEVEL
SHIFTER
FIGURE 14. TYPICAL TV APPLICATION CIRCUIT
1.0μF
1.0μF
DC/DC
CONVERTER
TIMING
CONTROLLER
LCD PANEL
1.0μF
V
ON1
V
ON2
V
OFF
ISL24011
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