17 FN8273.1 September 5, 2013 FIGURE 30. TIMING DIAGRAM FOR READING AFTER " />
參數(shù)資料
型號: ISL26320FBZ-T
廠商: Intersil
文件頁數(shù): 9/23頁
文件大?。?/td> 0K
描述: IC ADC 12BIT SPI/SRL 250K 8SOIC
標準包裝: 2,500
位數(shù): 12
采樣率(每秒): 250k
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 80mW
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極
ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329
17
FN8273.1
September 5, 2013
FIGURE 30. TIMING DIAGRAM FOR READING AFTER CONVERSION MODE, WITHOUT EOC
FIGURE 31. TIMING DIAGRAM FOR READING DURING CONVERSION MODE, WITHOUT EOC
FIGURE 32. TIMING DIAGRAM FOR READING SPANNING CONVERSION MODE, WITHOUT EOC
Acq.
Acquisition
CNV
SCLK
SDI
SDO
MSB
MSB-1
D15
D14
. . .
D1
LSB
D5
D4
ADC STATE
Idle
Power-Up
Acquisition
Conversion
Idle
tACQ
tSCLK
tSDO_V
tSCLKL
Conversion N+1
Configuration N+1
Conversion Result N-1
tSCLKH
MSB
MSB-1
D15
D14
. . .
LSB
Configuration N+2
Conversion Result N
Conversion
Idle
tSDOZ_D
tCNV_SCLK
tSDI_H
tSDI_SU
Hi-Z State
Conversion N
D5
D4
Idle
CNV
SCLK
SDI
SDO
D15
D14
. . .
D14
. . .
ADC STATE
Idle
Power-Up
Acquisition
Conversion
Idle
Acquisition
Conversion
tACQ
tSCLK
tCNV_CLK
tSCLKL
tDATA
tCNV
Conversion N
Conversion N+1
Configuration N+1
Conversion Result N-1
Configuration N+2
Conversion Result N
tSCLKH
MSB
MSB-1
D1
LSB
MSB
MSB-1
D1
tSDO_V
tSDI_H
tSDI_SU
Hi-Z State
D5
D4
D5
D4
Idle
CNV
SCLK
SDI
SDO
D15
D14
. . .
D4
ADC STATE
Idle
Power-Up
Acquisition
Conversion
Acquisition
Conversion
tACQ
tSCLK
tCNV_SCLK
tSCLKL
tDATA
tCNV
Conversion N
Conversion N+1
Configuration N+1
Conversion Result N-1
Configuration N+2
Conversion Result N
tSCLKH
D12
MSB
MSB-1
D1
LSB
D13
Hi-Z State
MSB
MSB-1
D1
tSDO_V
tSDI_H
tSDI_SU
D15
D14
D4
. . .
MSB-1 MSB-2
. . .
Note: Transition from Acquisition to Conversion mode may occur after any integer number of clock cycles (provided that the minimum tACQ is satisfied).
. . .
D12
D13
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