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| 型號(hào)： | ISL26708IHZ-T |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 5/21頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT SPI/SRL 1M 8-SOT-23 |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 8.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極 |
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ISL26712, ISL26710, ISL26708
13
FN7999.3
September 5, 2012
Functional Description
The ISL26712/10/08 are based on a successive approximation
register (SAR) architecture utilizing capacitive charge
redistribution digital-to-analog converters (DACs). Figure 24
shows a simplified representation of the converter. During the
acquisition phase (ACQ), the differential input is stored on the
sampling capacitors (CS). The comparator is in a balanced state
since the switch across its inputs is closed. The signal is fully
acquired after tACQ has elapsed and the switches then transition
to the conversion phase (CONV) so the stored voltage may be
converted to digital format. The comparator will become
unbalanced when the differential switch opens and the input
switches transition (assuming that the stored voltage is not
exactly at mid-scale). The comparator output reflects whether the
stored voltage is above or below mid-scale, which sets the value
of the MSB. The SAR logic then forces the capacitive DACs to
adjust up or down by one quarter of full-scale by switching in
binarily weighted capacitors. Again, the comparator output
reflects whether the stored voltage is above or below the new
value, setting the value of the next lowest bit. This process
repeats until all 12 bits have been resolved.
An external clock must be applied to the SCLK pin to generate a
conversion result. The allowable frequency range for SCLK is
10kHz to 18MHz (556SPS to 1MSPS). Serial output data is
transmitted on the falling edge of SCLK. The receiving device
(FPGA, DSP or Microcontroller) may latch the data on the rising
edge of SCLK to maximize set-up and hold times.
A stable, low-noise reference voltage must be applied to the
VREF pin to set the full-scale input range and common-mode
voltage. See “Voltage Reference Input” on page 14 for more
details.
ADC Transfer Function
The output coding for the ISL26712/10/08 is twos complement.
The first code transition occurs at successive LSB values (i.e.,
1 LSB, 2 LSB, and so on). The LSB size of the ISL26712 is
2*VREF/4096, while the LSB size of the ISL26710 is
2*VREF/1024 and the ISL26708 is 2*VREF/512. The ideal
transfer characteristic of the ISL26712/10/08 is shown in
Figure 25.
Analog Input
The ISL26712/10/08 feature a fully differential input with a
nominal full-scale range equal to twice the applied VREF voltage.
Each input swings VREF VP-P, 180° out-of-phase from one
another for a total differential input of 2*VREF (refer to
Figure 26).
Differential signaling offers several benefits over a single-ended
input, such as:
Doubling of the full-scale input range (and therefore the
dynamic range)
Improved even order harmonic distortion
Better noise immunity due to common mode rejection
Figure 27 shows the relationship between the reference voltage
and the full-scale input range for two different values of VREF.
Note that there is a trade-off between VREF and the allowable
common mode input voltage (VCM). The full-scale input range is
proportional to VREF; therefore the VCM range must be limited
for larger values of VREF in order to keep the absolute maximum
and minimum voltages on the AIN+ and AIN– pins within
and 3V operation, respectively. The dashed lines show the
theoretical VCM range based solely on keeping the AIN+ and
AIN– pins within the supply rails. Additional restrictions are
imposed due to the required headroom of the input circuitry,
resulting in practical limits shown by the shaded area.
FIGURE 24. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
AIN+
AIN–
VREF
ACQ
CONV
ACQ
CONV
DA
C
D
A
C
SAR
LOGIC
CS
1LSB = 2VREF/4096
100...000
100...001
100...010
111...111
000...000
000...001
011...110
011...111
AD
C
CO
DE
ANALOG INPUT
AIN+ – (AIN–)
–VREF
+ LSB
+VREF
– 1LSB
0V
+VREF
– 1LSB
FIGURE 25. IDEAL TRANSFER CHARACTERISTICS
FIGURE 26. DIFFERENTIAL INPUT SIGNALING
VCM
VREF(P-P)
AIN+
AIN–
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參數(shù)描述 |
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| ISL26708IHZ-T7A | 功能描述:IC ADC 8BIT SPI/SRL 1M 8SOT-23 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):10 采樣率（每秒）:357k 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:830µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:10-TDFN-EP（3x3） 包裝:剪切帶 (CT) 輸入數(shù)目和類型:2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極 產(chǎn)品目錄頁(yè)面:1396 (CN2011-ZH PDF) 其它名稱:MAX1395ETB+TCT |
| ISL26708IRTZ | 功能描述:IC ADC 8BIT SAR 1MSPS 8-TDFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| ISL26708IRTZ-T | 功能描述:IC ADC 8BIT SAR 1MSPS 8-TDFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| ISL26708IRTZ-T7A | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 08 BIT 1MSPS SAR ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ISL26710 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 10-Bit and 8-Bit, 1MSPS SAR ADCs |
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