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參數(shù)資料
| 型號： | ISL267440IUZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE |
| 標準包裝： | 980 |
| 系列： | * |
ISL267440, ISL267450A
15
FN7708.2
June 28, 2012
Data Format
Output data is encoded in two’s complement format as shown in
Table 1. The voltage levels in the table are idealized and don’t
account for any gain/offset errors or noise.
Terminology
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fs/2), excluding DC. The ratio
is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
Thus, for a 12-bit converter this is 74dB, and for a 10-bit this is 62dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the ISL267440, ISL267450A,
it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second to the
sixth harmonics.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding DC) to the rms value of
the fundamental (also referred to as Spurious Free Dynamic
Range (SFDR)). Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will be
a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m and n = 0, 1, 2 or 3. Intermodulation distortion terms are those
for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb).
The ISL267440, ISL267450A is tested using the CCIF standard,
where two input frequencies near the top end of the input
bandwidth are used. In this case, the second order terms are
usually distanced in frequency from the original sine waves,
while the third order terms are usually at a frequency close to the
input frequencies. As a result, the second and third order terms
are specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
Aperture Delay
This is the amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Aperture Jitter
This is the sample-to-sample variation in the effective point in
time at which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input.
Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power of
a 250mVP-P sine wave applied to the common-mode voltage of
VIN+ and VIN– of frequency fs:
Pf is the power at the frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Zero-Code Error
This is the deviation of the midscale code transition (111...111 to
000...000) from the ideal VIN+ – VIN– (i.e., 0 LSB).
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal VIN+ – VIN– (i.e., +REF – 1 LSB), after
the zero code error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal VIN+ – VIN– (i.e., – REF + 1 LSB), after
the zero code error has been adjusted out.
TABLE 1. TWO’S COMPLEMENT DATA FORMATTING
INPUT
VOLTAGE
DIGITAL OUTPUT
–Full Scale
–VREF
1000 0000 0000
–Full Scale + 1LSB
–VREF+ 1LSB
1000 0000 0001
Midscale
0
0000 0000 0000
+Full Scale – 1LSB
+VREF– 1LSB
0111 1111 1110
+Full Scale
+VREF
0111 1111 1111
Signal-to-(Noise + Distortion)
6.02 N
1.76
+
()dB
=
(EQ. 1)
(EQ. 2)
THD dB
()
20
V
2
V
3
2
V
4
2
V
5
2
V
6
2
++
V
1
2
------------------------------------------------------------------------
log
=
(EQ. 3)
CMRR dB
()
10
Pfl Pfs
()
log
=
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| ISL267440IUZ-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10 BIT 1MSPS SAR ADC 8LD 3 X 3 PROPRIETRY RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ISL267440IUZ-T7A | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10 BIT 1MSPS SAR ADC IN 8LD RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ISL267450 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 1MSPS SAR ADCs |
| ISL267450AIHZ-T | 功能描述:IC ADC 12BIT SPI/SRL 8-SOT-23 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| ISL267450AIHZ-T7A | 功能描述:IC ADC 12BIT SPI/SRL 1M 8SOT-23 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 位數(shù):10 采樣率（每秒）:357k 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:830µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:10-TDFN-EP（3x3） 包裝:剪切帶 (CT) 輸入數(shù)目和類型:2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極 產(chǎn)品目錄頁面:1396 (CN2011-ZH PDF) 其它名稱:MAX1395ETB+TCT |
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